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74LVTH18502APMRG4 PDF预览

74LVTH18502APMRG4

更新时间： 2024-11-05 04:06:35
品牌 Logo 应用领域
德州仪器 - TI 总线收发器测试
页数 文件大小 规格书
40页 785K
描述
3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

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74LVTH18502APMRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP, QFP64,.47SQ,20针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.48其他特性：SUPPORTS IEEE STANDARD 1149.1-1990 BOUNDARY SCAN
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVTJESD-30 代码：S-PQFP-G64
JESD-609代码：e4长度：10 mm
逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER最大I（ol）：0.032 A
湿度敏感等级：3位数：9
功能数量：2端口数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP64,.47SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：24 mA
Prop。Delay @ Nom-Sup：4.9 ns传播延迟（tpd）：6.8 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：10 mm

74LVTH18502APMRG4 数据手册

 浏览型号74LVTH18502APMRG4的Datasheet PDF文件第2页浏览型号74LVTH18502APMRG4的Datasheet PDF文件第3页浏览型号74LVTH18502APMRG4的Datasheet PDF文件第4页浏览型号74LVTH18502APMRG4的Datasheet PDF文件第5页浏览型号74LVTH18502APMRG4的Datasheet PDF文件第6页浏览型号74LVTH18502APMRG4的Datasheet PDF文件第7页 
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SCBS668C − JULY 1996 − REVISED JUNE 2004  
D
D
D
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Members of the Texas Instruments  
WidebusFamily  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
D
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
D
SCOPE Instruction Set  
− IEEE Standard 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
and Output Voltages With 3.3-V V  
)
CC  
− Parallel-Signature Analysis at Inputs  
− Pseudorandom Pattern Generation From  
Outputs  
− Sample Inputs/Toggle Outputs  
− Binary Count From Outputs  
− Device Identification  
D
D
Support Unregulated Battery Operation  
Down to 2.7 V  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
− Even-Parity Opcodes  
D
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup Resistors  
D
Packaged in 64-Pin Plastic Thin Quad Flat  
(PM) Packages Using 0.5-mm  
Center-to-Center Spacings and 68-Pin  
Ceramic Quad Flat (HV) Packages Using  
25-mil Center-to-Center Spacings  
B-Port Outputs of ’LVTH182502A Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
description  
The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members  
of the Texas Instruments SCOPEtestability integrated-circuit family. This family of devices supports IEEE  
Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to  
the test circuitry is accomplished via the 4-wire test access port (TAP) interface.  
Additionally, these devices are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and  
D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes. Another use is as two  
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot  
samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating  
the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.  
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),  
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when  
LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.  
Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the  
B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is  
similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.  
In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry  
is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs  
boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and UBT are trademarks of Texas Instruments.  
Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...40

中文翻译

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74LVTH18502APMRG4 替代型号

型号 品牌 替代类型 描述 数据表
8V18502AIPMREP TI

完全替代

 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
V62/04729-01XE TI

完全替代

 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18502APMG4 TI

完全替代

 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

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