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74LVTH2240WM PDF预览

74LVTH2240WM

更新时间: 2024-11-17 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
6页 80K
描述
Low Voltage Inverting Octal Buffer/Line Driver with 3-STATE Outputs

74LVTH2240WM 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SO-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.29
Is Samacsys:N控制类型:ENABLE LOW
系列:LVTJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:4.4 ns
传播延迟(tpd):4.4 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

74LVTH2240WM 数据手册

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July 1999  
Revised August 1999  
74LVT2240 • 74LVTH2240  
Low Voltage Inverting Octal Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVT2240 and LVTH2240 are inverting octal buffers  
and line drivers designed to be employed as memory  
address drivers, clock drivers and bus oriented transmitters  
or receivers which provides improved PC board density.  
The equivalent 25-Series resistors helps reduce output  
overshoot and undershoot.  
5V VCC  
Equivalent 25-Series resistors on outputs  
Bushold data inputs eliminate the need for external pull-  
up resistors to hold unused inputs (74LVTH2240), also  
available without bushold feature (74LVT2240).  
The LVTH2240 data inputs include bushold, eliminating the  
need for external pull-up resistors to hold unused inputs.  
Live insertion/extraction permitted  
Power Up/Down high impedance provides glitch-free  
bus loading  
These inverting octal buffers and line drivers are designed  
for low-voltage (3.3V) VCC applications, but with the capa-  
Outputs source/sink 12 mA/+12 mA  
Latch-up performance exceeds 500 mA  
bility to provide a TTL interface to a 5V environment. The  
LVT2240 and LVTH2240 are fabricated with an advanced  
BiCMOS technology to achieve high speed operation simi-  
lar to 5V ABT while maintaining low power dissipation.  
Ordering Code:  
Order Number  
74LVT2240WM  
74LVT2240SJ  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
M20D  
74LVT2240MTC  
74LVTH2240WM  
74LVTH2240SJ  
74LVTH2240MTC  
MTC20  
M20B  
M20D  
MTC20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS500212  
www.fairchildsemi.com  

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