Datasheet > 74LVCH2T45GT,115

74LVCH2T45GT,115

更新时间： 2024-09-13 18:05:19

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管逻辑集成电路
页数	文件大小	规格书
32页	291K
描述
74LVC2T45; 74LVCH2T45 - Dual supply translating transceiver; 3-state SON 8-Pin

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74LVCH2T45GT,115 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	SON
包装说明：	1 X 1.95 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-252, SOT833-1, SON-8	针数：	8
Reach Compliance Code：	compliant	风险等级：	5.78
Base Number Matches：	1

74LVCH2T45GT,115 数据手册

74LVC2T45; 74LVCH2T45

Dual supply translating transceiver; 3-state

Rev. 03 — 19 January 2010

Product data sheet

1. General description

The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with

3-state outputs that enable bidirectional level translation. They feature two data

input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V_CC(A)

and V_CC(B)). Both V_CC(A)and V_CC(B)can be supplied at any voltage between 1.2 V and

5.5 V making the device suitable for translating between any of the low voltage nodes

(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to V_CC(A)and

pins nB are referenced to V_CC(B). A HIGH on DIR allows transmission from nA to nB and a

LOW on DIR allows transmission from nB to nA.

The devices are fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mode when either V_CC(A)or V_CC(B)are at

GND level, both A port and B port are in the high-impedance OFF-state.

Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid

logic level.

2. Features

Wide supply voltage range:

V_CC(A): 1.2 V to 5.5 V

V_CC(B): 1.2 V to 5.5 V

High noise immunity

Complies with JEDEC standards:

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

ESD protection:

HBM JESD22-A114E Class 3A exceeds 4000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

Maximum data rates:

420 Mbps (3.3 V to 5.0 V translation)

210 Mbps (translate to 3.3 V))

140 Mbps (translate to 2.5 V)

75 Mbps (translate to 1.8 V)

60 Mbps (translate to 1.5 V)

12 3 4 5 6 7...32

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与74LVCH2T45GT,115相关器件

型号	品牌	获取价格	描述	数据表
74LVCH2T45-Q100	NEXPERIA	获取价格	Dual supply translating transceiver; 3-state
74LVCH322244A	NXP	获取价格	32-bit buffer/line driver; with 30 ohm series termination resistors; 5 V input/output tole
74LVCH322244AEC	NXP	获取价格	32-bit buffer/line driver; with 30 ohm series termination resistors; 5 V input/output tole
74LVCH322244AEC/G	NXP	获取价格	IC LVC/LCX/Z SERIES, OCTAL 4-BIT DRIVER, TRUE OUTPUT, PBGA96, 13.50 X 5.50 MM, 1.05 MM HEI
74LVCH322244AEC;55	NXP	获取价格	74LVCH322244A - 32-bit buffer/line driver; wi
74LVCH322244AEC-S	NXP	获取价格	IC LVC/LCX/Z SERIES, OCTAL 4-BIT DRIVER, TRUE OUTPUT, PBGA96, 13.50 X 5.50 X 1.05 MM, PLAS
74LVCH322244AZKER	TI	获取价格	32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
74LVCH322245A	NXP	获取价格	32-bit bus transceiver with direction pin; 30 ohm series termination resistors; 5 V tolera
74LVCH322245AEC	NXP	获取价格	32-bit bus transceiver with direction pin; 30 ohm series termination resistors; 5 V tolera
74LVCH322245AEC,51	NXP	获取价格	74LVCH322245A - 32-bit bus transceiver with d

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