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74LVCH16541ADL,112 PDF预览

74LVCH16541ADL,112

更新时间: 2024-11-04 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
15页 116K
描述
74LVCH16541A - 16-bit buffer/line driver; 3-state SSOP 48-Pin

74LVCH16541ADL,112 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.16
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:15.875 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:BULK PACK
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:5.5 ns传播延迟(tpd):5.5 ns
认证状态:Not Qualified座面最大高度:2.8 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

74LVCH16541ADL,112 数据手册

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74LVCH16541A  
16-bit buffer/line driver; 3-state  
Rev. 3 — 15 February 2012  
Product data sheet  
1. General description  
The 74LVCH16541A is a 16-bit buffer/line driver with 3-state outputs. The 3-state outputs  
are controlled by the output enable inputs (1OEn and 2OEn). A HIGH on nOEn causes  
the outputs to assume a high-impedance OFF-state.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices in mixed 3.3 V and  
5 V applications.  
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused  
inputs.  
2. Features and benefits  
5 Volt tolerant inputs and outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low-power consumption  
MULTIBYTE flow-through standard pin-out architecture  
Low inductance multiple power and ground pins for minimum noise and ground  
bounce  
Direct interface with TTL levels  
High-impedance outputs when VCC = 0 V  
All data inputs have bus hold  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C.  
 
 

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