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74LVC2G17GW-T PDF预览

74LVC2G17GW-T

更新时间: 2024-02-11 07:38:40
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恩智浦 - NXP 触发器
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16页 91K
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74LVC2G17GW-T 数据手册

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74LVC2G17  
Dual non-inverting Schmitt trigger with 5 V tolerant input  
Rev. 04 — 9 October 2006  
Product data sheet  
1. General description  
The 74LVC2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device  
and superior to most advanced CMOS compatible TTL families.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger action. It is  
capable of transforming slowly changing input signals into sharply defined, jitter-free  
output signals.  
2. Features  
I Wide supply voltage range from 1.65 V to 5.5 V  
I 5 V tolerant input/output for interfacing with 5 V logic  
I High noise immunity  
I Complies with JEDEC standard:  
N JESD8-7 (1.65 V to 1.95 V)  
N JESD8-5 (2.3 V to 2.7 V)  
N JESD-8B/JESD36 (2.7 V to 3.6 V)  
I ESD protection:  
N HBM JESD22-A114-D exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I ±24 mA output drive (VCC = 3.0 V)  
I CMOS low-power consumption  
I Latch-up performance exceeds 250 mA  
I Direct interface with TTL levels  
I Multiple package options  
I Specified from 40 °C to +85 °C and 40 °C to +125 °C  
3. Applications  
I Wave and pulse shapers for highly noisy environments  

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