Datasheet > 74LVC2G240-Q100

74LVC2G240-Q100

更新时间： 2024-02-29 18:14:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	213K
描述
Dual inverting buffer/line driver; 3-state

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74LVC2G240-Q100 数据手册

74LVC2G240-Q100

Dual inverting buffer/line driver; 3-state

Rev. 3 — 1 November 2018

Product data sheet

1. General description

The 74LVC2G240-Q100 is a dual inverting buffer/line driver with 3-state outputs. The output enable

inputs 1OE and 2OE, control the 3-state outputs. A HIGH level at pins nOE causes the outputs to

assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly

tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC2G240-Q100 as a translator in a mixed 3.3 V and 5 V environment.

It is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry disables the

output, preventing a damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant input/output for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

±24 mA output drive (V_CC= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

12 3 4 5 6 7...13

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