Datasheet > 74LVC2G240DP,118

74LVC2G240DP,118

更新时间： 2024-11-16 14:37:23

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
22页	289K
描述
74LVC2G240 - Dual inverting buffer/line driver; 3-state TSSOP 8-Pin

阅读下载

中文翻译

获取价格

如果您发现信息不准确，欢迎纠错

74LVC2G240DP,118 技术参数

74LVC2G240

Dual inverting buffer/line driver; 3-state

Rev. 8 — 8 April 2013

Product data sheet

1. General description

The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state

outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at

pins nOE causes the outputs to assume a high-impedance OFF-state. Schmitt trigger

action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC2G240 as a translator in a mixed 3.3 V and 5 V environment.

It is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing a damaging backflow current through the device when it is

powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...22

中文翻译

下载PDF

型号	品牌	获取价格	描述	数据表
74LVC2G240DP-G	NXP	获取价格	暂无描述
74LVC2G240DP-Q100	NEXPERIA	获取价格	Dual inverting buffer/line driver; 3-state
74LVC2G240GM	NXP	获取价格	Dual inverting buffer/line driver; 3-state
74LVC2G240GN	NEXPERIA	获取价格	Dual inverting buffer/line driver; 3-stateProduction
74LVC2G240GS	NEXPERIA	获取价格	Dual inverting buffer/line driver; 3-stateProduction
74LVC2G240GT	NXP	获取价格	Dual inverting buffer/line driver; 3-state
74LVC2G240GT	NEXPERIA	获取价格	Dual inverting buffer/line driver; 3-stateProduction
74LVC2G240GT,115	NXP	获取价格	74LVC2G240 - Dual inverting buffer/line driver; 3-state SON 8-Pin
74LVC2G240GT-G	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, INVERTED OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGH
74LVC2G240-Q100	NEXPERIA	获取价格	Dual inverting buffer/line driver; 3-state