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74LVC1G14GM-Q100 PDF预览

74LVC1G14GM-Q100

更新时间: 2024-11-19 11:12:03
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
15页 248K
描述
Single Schmitt trigger inverterProduction

74LVC1G14GM-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VSON, SOLCC6,.04,20Reach Compliance Code:unknown
风险等级:5.57系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-N6JESD-609代码:e4
长度:1.45 mm逻辑集成电路类型:INVERTER
湿度敏感等级:1功能数量:1
输入次数:1端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装等效代码:SOLCC6,.04,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE最大电源电流(ICC):0.004 mA
Prop。Delay @ Nom-Sup:14 ns传播延迟(tpd):14 ns
施密特触发器:YES筛选级别:AEC-Q100
座面最大高度:0.5 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL宽度:1 mm
Base Number Matches:1

74LVC1G14GM-Q100 数据手册

 浏览型号74LVC1G14GM-Q100的Datasheet PDF文件第2页浏览型号74LVC1G14GM-Q100的Datasheet PDF文件第3页浏览型号74LVC1G14GM-Q100的Datasheet PDF文件第4页浏览型号74LVC1G14GM-Q100的Datasheet PDF文件第5页浏览型号74LVC1G14GM-Q100的Datasheet PDF文件第6页浏览型号74LVC1G14GM-Q100的Datasheet PDF文件第7页 
74LVC1G14-Q100  
Single Schmitt trigger inverter  
Rev. 7 — 20 January 2022  
Product data sheet  
1. General description  
The 74LVC1G14-Q100 is a single inverter with Schmitt-trigger inputs. Inputs can be driven from  
either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed  
3.3 V and 5 V environments. This device is fully specified for partial power down applications using  
IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current  
through the device when it is powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 1.65 V to 5.5 V  
Overvoltage tolerant inputs to 5.5 V  
High noise immunity  
CMOS low power dissipation  
IOFF circuitry provides partial Power-down mode operation  
±24 mA output drive (VCC = 3.0 V)  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Unlimited rise and fall times  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)  
Multiple package options  
3. Applications  
Wave and pulse shaper  
Astable multivibrator  
Monostable multivibrator  
 
 
 

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