Datasheet > 74LVC1G14GS

74LVC1G14GS

更新时间： 2024-11-19 01:07:47

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
20页	368K
描述
Single Schmitt-trigger inverter

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74LVC1G14GS 数据手册

74LVC1G14

Single Schmitt-trigger inverter

Rev. 12 — 6 August 2012

Product data sheet

1. General description

The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is

capable of transforming slowly changing input signals into sharply defined, jitter-free

output signals.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at the input

makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V).

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Unlimited rise and fall times

 Input accepts voltages up to 5 V

 Multiple package options

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V.

 Specified from 40 C to +85 C and 40 C to +125 C.

3. Applications

 Wave and pulse shaper

 Astable multivibrator

 Monostable multivibrator

12 3 4 5 6 7...20

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