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74LVC162373ADGG PDF预览

74LVC162373ADGG

更新时间： 2023-09-03 20:27:32
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
14页 241K
描述
16-bit D-type transparent latch; 30 Ohm series termination resistors; 5 V tolerant inputs/outputs; 3-stateProduction

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74LVC162373ADGG 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TSSOP, TSSOP48,.3,20Reach Compliance Code：unknown
风险等级：5.66Is Samacsys：N
JESD-30 代码：R-PDSO-G48负载电容（CL）：50 pF
逻辑集成电路类型：D LATCH最大I（ol）：0.012 A
位数：8功能数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：3.3 V
Prop。Delay @ Nom-Sup：5.4 ns认证状态：Not Qualified
子类别：FF/Latches标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
Base Number Matches：1

74LVC162373ADGG 数据手册

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74LVC162373A; 74LVCH162373A  
16-bit D-type transparent latch; 30 Ω series termination  
resistors; 5 V tolerant inputs/outputs; 3-state  
Rev. 6 — 16 September 2021  
Product data sheet  
1. General description  
The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 Ω  
termination resistors and 3-state outputs. The 74LVCH162373A has separate D-type inputs with  
bus hold for each latch. Both devices can be used as two 8-bit transparent latches or a single 16-  
bit transparent latch. Both devices feature two latch enables (1LE and 2LE) and two output enables  
(1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches.  
In this condition the latches are transparent, a latch output will change each time its corresponding  
D-input changes. When nLE is LOW the latches store the information that was present at the inputs  
a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to  
assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the  
latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in mixed 3.3 V and 5 V environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
These devices are fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the devices  
when they are powered down.  
2. Features and benefits  
•
Overvoltage tolerant inputs to 5.5 V  
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Multibyte flow-through standard pinout architecture  
Multiple low inductance supply pins for minimum noise and ground bounce  
Direct interface with TTL levels  
All data inputs have bus hold (74LVCH162373A only)  
IOFF circuitry provides partial Power-down mode operation  
Complies with JEDEC standard:  
•
•
•
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
•
ESD protection:  
•
•
•
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC162373ADGG  
74LVCH162373ADGG  
-40 °C to +125 °C  
TSSOP48  
plastic thin shrink small outline package;  
48 leads; body width 6.1 mm  
SOT362-1  
 
 
 
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