Datasheet > 74LVC162373ADGG

74LVC162373ADGG

更新时间： 2024-11-22 11:10:31

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
14页	241K
描述
16-bit D-type transparent latch; 30 Ohm series termination resistors; 5 V tolerant inputs/outputs; 3-stateProduction

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74LVC162373ADGG 数据手册

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination

resistors; 5 V tolerant inputs/outputs; 3-state

Rev. 6 — 16 September 2021

Product data sheet

1. General description

The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 Ω

termination resistors and 3-state outputs. The 74LVCH162373A has separate D-type inputs with

bus hold for each latch. Both devices can be used as two 8-bit transparent latches or a single 16-

bit transparent latch. Both devices feature two latch enables (1LE and 2LE) and two output enables

(1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches.

In this condition the latches are transparent, a latch output will change each time its corresponding

D-input changes. When nLE is LOW the latches store the information that was present at the inputs

a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to

assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the

latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

These devices are fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the devices

when they are powered down.

2. Features and benefits

•

Overvoltage tolerant inputs to 5.5 V

•

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Multibyte flow-through standard pinout architecture

Multiple low inductance supply pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold (74LVCH162373A only)

I_OFFcircuitry provides partial Power-down mode operation

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-B exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC162373ADGG

74LVCH162373ADGG

-40 °C to +125 °C

TSSOP48

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

SOT362-1

12 3 4 5 6 7...14

中文翻译

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与74LVC162373ADGG相关器件

型号	品牌	获取价格	描述	数据表
74LVC162373ADGG:51	NXP	获取价格	74LVC(H)162373A - 16-bit D-type transparent latch TSSOP 48-Pin
74LVC162373ADGG-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVC162373ADL	NXP	获取价格	16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output
74LVC162373ADL,112	NXP	获取价格	74LVC(H)162373A - 16-bit D-type transparent latch SSOP 48-Pin
74LVC162373ADL,118	NXP	获取价格	74LVC(H)162373A - 16-bit D-type transparent latch SSOP 48-Pin
74LVC162374A	NXP	获取价格	16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/
74LVC162374ADGG	NXP	获取价格	16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/
74LVC162374ADGG-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVC162374ADL	NXP	获取价格	16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/
74LVC162374ADL-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver

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