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74LVC16240ADGG-Q100 PDF预览

74LVC16240ADGG-Q100

更新时间: 2023-09-03 20:30:55
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
12页 203K
描述
16-bit buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-stateProduction

74LVC16240ADGG-Q100 技术参数

生命周期:Transferred包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.62其他特性:SEIGHTED-HGT NOM
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G48
长度:12.5 mm逻辑集成电路类型:BUS DRIVER
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):11.7 ns筛选级别:AEC-Q100
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmBase Number Matches:1

74LVC16240ADGG-Q100 数据手册

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74LVC16240A-Q100  
16-bit buffer/line driver with 5 V tolerant inputs/outputs;  
inverting; 3-state  
Rev. 2 — 25 April 2019  
Product data sheet  
1. General description  
The 74LVC16240A-Q100 is a 16-bit inverting buffer/line driver with 3-state outputs. The device can  
be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output  
enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE  
causes the outputs to assume a high-impedance OFF-state.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to  
the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.  
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing the damaging backflow current through the device when it is  
powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
MULTIBYTE flow-through standard pinout architecture  
Low inductance multiple power and ground pins for minimum noise and ground bounce  
Direct interface with TTL levels  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC16240ADGG-Q100 -40 °C to +125 °C  
TSSOP48  
plastic thin shrink small outline package;  
48 leads; body width 6.1 mm  
SOT362-1  
 
 
 

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