Datasheet > 74LVC162373ADGG-T

74LVC162373ADGG-T

更新时间： 2024-11-26 05:33:07

品牌	Logo	应用领域
恩智浦 - NXP		驱动光电二极管输出元件逻辑集成电路
页数	文件大小	规格书
18页	126K
描述
IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver

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74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30  series termination

resistors; 5 V tolerant inputs/outputs; 3-state

Rev. 4 — 14 May 2013

Product data sheet

1. General description

The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with

separate D-type inputs with bus hold (74LVCH162373A only) for each latch and 3-state

outputs for bus-oriented applications. One latch enable (pin nLE) input and one output

enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V

devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow

the use of these devices in mixed 3.3 V and 5 V applications. The device consists of two

sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is

HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition,

the latches are transparent, that is, the latch output changes each time its corresponding

data inputs changes. When pin nLE is LOW, the latches store the information that was

present at the data inputs a set-up time preceding the HIGH to LOW transition of pin

nLE.When pin nOE is LOW, the contents of the eight latches are available at the outputs.

When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the

nOE input does not affect the state of the latches.

The device is designed with 30  series termination resistors in both HIGH and LOW

output stages to reduce line noise. Bus hold on data inputs eliminates the need for

external pull-up resistors to hold unused inputs.

2. Features and benefits

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Multibyte flow-through standard pinout architecture

 Multiple low inductance supply pins for minimum noise and ground bounce

 Direct interface with TTL levels

 All data inputs have bus hold (74LVCH162373A only)

 High-impedance when V_CC= 0 V

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

12 3 4 5 6 7...18

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与74LVC162373ADGG-T相关器件

型号	品牌	获取价格	描述	数据表
74LVC162373ADL	NXP	获取价格	16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output
74LVC162373ADL,112	NXP	获取价格	74LVC(H)162373A - 16-bit D-type transparent latch SSOP 48-Pin
74LVC162373ADL,118	NXP	获取价格	74LVC(H)162373A - 16-bit D-type transparent latch SSOP 48-Pin
74LVC162374A	NXP	获取价格	16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/
74LVC162374ADGG	NXP	获取价格	16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/
74LVC162374ADGG-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVC162374ADL	NXP	获取价格	16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/
74LVC162374ADL-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVC162374APA	IDT	获取价格	TSSOP-48, Tube
74LVC162374APF	IDT	获取价格	TVSOP-48, Tube

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