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74LCX574 PDF预览

74LCX574

更新时间: 2024-11-24 22:56:19
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意法半导体 - STMICROELECTRONICS 触发器输出元件输入元件
页数 文件大小 规格书
13页 268K
描述
OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

74LCX574 数据手册

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74LCX574  
OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE)  
WITH 5V TOLERANT INPUTS AND OUTPUTS  
5V TOLERANT INPUTS AND OUTPUTS  
HIGH SPEED:  
f
= 150 MHz (MIN.) at V = 3V  
MAX  
CC  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 24mA (MIN) at V = 3V  
OH  
OL  
CC  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2.0V to 3.6V (1.5V Data  
T & R  
V
CC  
SOP  
74LCX574MTR  
74LCX574TTR  
Retention)  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 574  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
outputs will be set to the logic state that were  
setup at the D inputs.  
While the (OE) input is low, the 8 outputs will be in  
a normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state.  
MM > 200V  
The Output control does not affect the internal  
operation of flip flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
It has same speed performance at 3.3V than 5V  
AC/ACT family, combined with a lower power  
consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LCX574 is a low voltage CMOS OCTAL  
D-TYPE FLIP FLOP with 3 STATE OUTPUT  
NON-INVERTING fabricated with sub-micron  
2
silicon gate and double-layer metal wiring C MOS  
technology. It is ideal for low power and high  
speed 3.3V applications; it can be interfaced to 5V  
signal environment for both inputs and outputs.  
These 8 bit D-Type flip-flops are controlled by a  
clock input (CK) and an output enable input (OE).  
On the positive transition of the clock, the Q  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/13  
September 2004  

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