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74LCX646

更新时间: 2024-11-16 22:56:19
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飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
10页 107K
描述
Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs

74LCX646 数据手册

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February 1994  
Revised March 2001  
74LCX646  
Low Voltage Octal Transceiver/Register  
with 5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX646 consists of registered bus transceiver circuits,  
D-type flip-flops, and control circuitry providing multiplexed  
transmission of data directly from the input bus or from the  
internal storage registers. Data on the A or B bus will be  
loaded into the respective registers on the LOW-to-HIGH  
transition of the appropriate pin (CPAB or CPBA) (see  
Functional Description).  
2.3V 3.6V VCC specifications provided  
7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA output drive (VCC = 3.0V)  
The LCX646 is designed for low voltage (2.5V or 3.3V) VCC  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
applications with capability of interfacing to a 5V signal  
environment.  
The LCX646 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to VCC through a pull-up resistor: the minimum value or the  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX646WM  
74LCX646MSA  
74LCX646MTC  
M24B  
MSA24  
MTC24  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
A0A7  
Description  
Data Register A Inputs  
Data Register A Outputs  
Data Register B Inputs  
Data Register B Outputs  
Clock Pulse Inputs  
B0B7  
CPAB, CPBA  
SAB, SBA  
OE  
Transmit/Receive Inputs  
Output Enable Input  
DIR  
Direction Control Input  
© 2001 Fairchild Semiconductor Corporation  
DS011997  
www.fairchildsemi.com  

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