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74HCT574DB,118

更新时间： 2024-01-02 00:29:09
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 57K
描述
74HC(T)574 - Octal D-type flip-flop; positive edge-trigger; 3-state SSOP2 20-Pin

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74HCT574DB,118 技术参数

是否Rohs认证： 符合生命周期：Not Recommended
零件包装代码：SSOP2包装说明：SSOP,
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.17
其他特性：BROADSIDE VERSION OF 374系列：HCT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：7.2 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：50 ns
认证状态：Not Qualified座面最大高度：2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：5.3 mm
Base Number Matches：1

74HCT574DB,118 数据手册

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Philips Semiconductors  
Product specification  
Octal D-type flip-flop; positive  
edge-trigger; 3-state  
74HC/HCT574  
The 8 flip-flops will store the state of  
their individual D-inputs that meet the  
set-up and hold time requirements on  
the LOW-to-HIGH CP transition.  
When OE is LOW, the contents of the  
8 flip-flops are available at the  
outputs.  
When OE is HIGH, the outputs go to  
the high impedance OFF-state.  
Operation of the OE input does not  
affect the state of the flip-flops.  
FEATURES  
GENERAL DESCRIPTION  
• 3-state non-inverting outputs for  
bus oriented applications  
The 74HC/HCT574 are high-speed  
Si-gate CMOS devices and are pin  
compatible with low power Schottky  
TTL (LSTTL). They are specified in  
compliance with JEDEC standard  
no. 7A.  
• 8-bit positive edge-triggered  
register  
• Common 3-state output enable  
input  
The 74HC/HCT574 are octal D-type  
flip-flops featuring separate D-type  
inputs for each flip-flop and  
non-inverting 3-state outputs for bus  
oriented applications. A clock (CP)  
and an output enable (OE) input are  
common to all flip-flops.  
• Independent register and 3-state  
buffer operation  
• Output capability: bus driver  
• ICC category: MSI  
The “574” is functionally identical to  
the “564”, but has non-inverting  
outputs.  
The “574” is functionally identical to  
the “374”, but has a different pinning.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
UNIT  
SYMBOL  
PARAMETER  
CONDITIONS  
HC  
HCT  
tPHL/ tPLH  
fmax  
propagation delay CP to Qn  
maximum clock frequency  
input capacitance  
CL = 15 pF; VCC = 5 V  
14  
15  
76  
3.5  
25  
ns  
123  
3.5  
22  
MHz  
pF  
CI  
CPD  
power dissipation capacitance per flip-flop  
notes 1 and 2  
pF  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
∑ (CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC − 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2
1234567

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