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74HCT4052D PDF预览

74HCT4052D

更新时间: 2024-11-25 11:12:03
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管
页数 文件大小 规格书
25页 370K
描述
Dual 4-channel analog multiplexer/demultiplexerProduction

74HCT4052D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP-16Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:4 weeks
风险等级:5.55Samacsys Confidence:3
Samacsys Status:ReleasedSamacsys PartID:170479
Samacsys Pin Count:16Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:SOT109-1 (MS-012)
Samacsys Released Date:2015-04-13 16:48:28Is Samacsys:N
模拟集成电路 - 其他类型:DIFFERENTIAL MULTIPLEXERJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
湿度敏感等级:1负电源电压最大值(Vsup):-5 V
负电源电压最小值(Vsup):-1 V标称负供电电压 (Vsup):-4.5 V
信道数量:4功能数量:1
端子数量:16标称断态隔离度:50 dB
通态电阻匹配规范:6 Ω最大通态电阻 (Ron):195 Ω
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260座面最大高度:1.75 mm
最大供电电压 (Vsup):5 V最小供电电压 (Vsup):1 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
最长断开时间:57 ns最长接通时间:72 ns
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

74HCT4052D 数据手册

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74HC4052; 74HCT4052  
Dual 4-channel analog multiplexer/demultiplexer  
Rev. 14 — 9 February 2023  
Product data sheet  
1. General description  
The 74HC4052; 74HCT4052 is a dual single-pole quad-throw analog switch (2 × SP4T) suitable  
for use in analog or digital 4:1 multiplexer/demultiplexer applications. Each switch features four  
independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital  
enable input (E) and two digital select inputs (S0 and S1) are common to both switches. When E  
is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide analog input voltage range from -5 V to +5 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Low ON resistance:  
80 Ω (typical) at VCC - VEE = 4.5 V  
70 Ω (typical) at VCC - VEE = 6.0 V  
60 Ω (typical) at VCC - VEE = 9.0 V  
Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals  
Typical ‘break before make’ built-in  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
Input levels:  
For 74HC4052: CMOS level  
For 74HCT4052: TTL level  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Applications  
Analog multiplexing and demultiplexing  
Digital multiplexing and demultiplexing  
Signal gating  
 
 
 

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