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74HCT193D

更新时间： 2024-11-05 11:11:43
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
24页 326K
描述
Presettable synchronous 4-bit binary up/down counterProduction

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74HCT193D 技术参数

是否Rohs认证：符合生命周期：Active
包装说明：SOP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.58
Is Samacsys：N其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
计数方向：BIDIRECTIONAL系列：HCT
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
湿度敏感等级：1位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260传播延迟（tpd）：65 ns
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：13 MHzBase Number Matches：1

74HCT193D 数据手册

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74HC193; 74HCT193  
Presettable synchronous 4-bit binary up/down counter  
Rev. 7 — 8 September 2021  
Product data sheet  
1. General description  
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down  
clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously  
with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held  
HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will  
count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior.  
The device can be cleared at any time by the asynchronous master reset input (MR); it may also  
be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up  
(TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached  
the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go  
LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,  
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The  
terminal count outputs can be used as the clock input signals to the next higher order circuit in  
a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be  
fully synchronous, since there is a slight delay time difference added for each stage that is added.  
The counter may be preset by the asynchronous parallel load capability of the circuit. Information  
present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs  
(Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW.  
A HIGH level on the master reset (MR) input will disable the parallel load gates, override both  
clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after  
a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a  
legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
•
Wide supply voltage range from 2.0 to 6.0 V  
•
•
•
•
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Input levels:  
•
•
For 74HC193: CMOS level  
For 74HCT193: TTL level  
•
•
•
•
•
Synchronous reversible 4-bit binary counting  
Asynchronous parallel load  
Asynchronous reset  
Expandable without external logic  
Complies with JEDEC standards:  
•
•
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
•
•
ESD protection:  
•
•
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V.  
Specified from -40 °C to +85 °C and -40 °C to +125 °C.  
 
 
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