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74HCT157D,652 PDF预览

74HCT157D,652

更新时间: 2024-11-04 14:32:23
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
19页 145K
描述
74HC(T)157 - Quad 2-input multiplexer SOP 16-Pin

74HCT157D,652 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:3.90 MM, PLASTIC, MS-012, SOT109-1, SO-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:8.09
系列:HCTJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
输出次数:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:41 ns
传播延迟(tpd):56 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Multiplexer/Demultiplexers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

74HCT157D,652 数据手册

 浏览型号74HCT157D,652的Datasheet PDF文件第2页浏览型号74HCT157D,652的Datasheet PDF文件第3页浏览型号74HCT157D,652的Datasheet PDF文件第4页浏览型号74HCT157D,652的Datasheet PDF文件第5页浏览型号74HCT157D,652的Datasheet PDF文件第6页浏览型号74HCT157D,652的Datasheet PDF文件第7页 
74HC157; 74HCT157  
Quad 2-input multiplexer  
Rev. 6 — 27 August 2012  
Product data sheet  
1. General description  
The 74HC157; 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.  
The 74HC/HCT157 are quad 2-input multiplexers which select 4 bits of data from two  
sources under the control of a common data select input (S). The enable input (E) is  
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of  
all other input conditions.  
Moving the data from two groups of registers to four common output buses is a common  
use of the 74HC/HCT157. The state of the common data select input (S) determines the  
particular register from which the data comes. It can also be used as function generator.  
The device is useful for implementing highly irregular logic by generating any four of the  
16 different functions of two variables with one variable common. The 74HC/HCT157 is  
logic implementation of a 4-pole, 2-position switch, where the position of the switch is  
determined by the logic levels applied to S.  
The logic equations are:  
1Y = E (1I1 S + 1I0 S)  
2Y = E (2I1 S + 2I0 S)  
3Y = E (3I1 S + 3I0 S)  
4Y = E (4I1 S + 4I0 S)  
The 74HC/HCT157 is identical to the 74HC158 but has non-inverting (true) outputs.  
2. Features and benefits  
Low-power dissipation  
Non-inverting data path  
ESD protection:  
HBM JESD22-A114F exceeds 2 000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from 40 C to +85 C and from 40 C to +125 C  
 
 

74HCT157D,652 替代型号

型号 品牌 替代类型 描述 数据表
74HCT157D NXP

完全替代

Quad 2-input multiplexer

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