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74HC573PW PDF预览

74HC573PW

更新时间： 2024-01-17 20:28:07
品牌 Logo 应用领域
恩智浦 - NXP 总线驱动器总线收发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
7页 65K
描述
Octal D-type transparent latch; 3-state

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74HC573PW 技术参数

Source Url Status Check Date：2013-06-14 00:00:00是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.09其他特性：BROADSIDE VERSION OF 373
系列：HC/UHJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：225 ns认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

74HC573PW 数据手册

 浏览型号74HC573PW的Datasheet PDF文件第1页浏览型号74HC573PW的Datasheet PDF文件第3页浏览型号74HC573PW的Datasheet PDF文件第4页浏览型号74HC573PW的Datasheet PDF文件第5页浏览型号74HC573PW的Datasheet PDF文件第6页浏览型号74HC573PW的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74HC/HCT573  
the Dn inputs enter the latches. In this  
condition the latches are transparent,  
i.e. a latch output will change state  
each time its corresponding D-input  
changes.  
FEATURES  
GENERAL DESCRIPTION  
• Inputs and outputs on opposite  
sides of package allowing easy  
interface with microprocessors  
The 74HC/HCT573 are high-speed  
Si-gate CMOS devices and are pin  
compatible with low power Schottky  
TTL (LSTTL). They are specified in  
compliance with JEDEC standard no.  
7A.  
• Useful as input or output port for  
microprocessors/microcomputers  
When LE is LOW the latches store the  
information that was present at the  
D-inputs a set-up time preceding the  
HIGH-to-LOW transition of LE.  
When OE is LOW, the contents of the  
8 latches are available at the outputs.  
When OE is HIGH, the outputs go to  
the high impedance OFF-state.  
• 3-state non-inverting outputs for  
bus oriented applications  
The 74HC/HCT573 are octal D-type  
transparent latches featuring  
separate D-type inputs for each latch  
and 3-state outputs for bus oriented  
applications.  
A latch enable (LE) input and an  
output enable (OE) input are common  
to all latches.  
• Common 3-state output enable  
input  
• Functionally identical to the “563”  
and “373”  
Operation of the OE input does not  
affect the state of the latches.  
• Output capability: bus driver  
• ICC category: MSI  
The “573” is functionally identical to  
the “563” and “373”, but the “563” has  
inverted outputs and the “373” has a  
different pin arrangement.  
The “573” consists of eight D-type  
transparent latches with 3-state true  
outputs. When LE is HIGH, data at  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
UNIT  
SYMBOL  
PARAMETER  
CONDITIONS  
HC  
HCT  
tPHL/ tPLH  
propagation delay  
Dn to Qn  
CL = 15 pF; VCC = 5 V  
14  
15  
3.5  
26  
17  
15  
3.5  
26  
ns  
ns  
pF  
pF  
LE to Qn  
CI  
input capacitance  
CPD  
power dissipation capacitance per latch notes 1 and 2  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
2
PD = CPD × VCC2 × fi +∑ (CL × VCC × fo) where:  
fi = input frequency in MHz; fo = output frequency in MHz  
∑ (CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF; VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2
1234567

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