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74HC3G16DP PDF预览

74HC3G16DP

更新时间: 2024-11-06 11:15:27
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
9页 179K
描述
Triple buffer gateProduction

74HC3G16DP 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP-8Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.76
系列:HC/UHJESD-30 代码:S-PDSO-G8
JESD-609代码:e4长度:3 mm
逻辑集成电路类型:BUFFER湿度敏感等级:1
功能数量:1输入次数:1
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):125 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

74HC3G16DP 数据手册

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74HC3G16  
Triple buffer gate  
Rev. 3 — 17 April 2019  
Product data sheet  
1. General description  
The 74HC3G16 is a triple buffer. Inputs include clamp diodes. This enables the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 V to 6.0 V  
CMOS input levels  
Complies with JEDEC standard no. 7 A  
Symmetrical output impedance  
High noise immunity  
Low-power dissipation  
Balanced propagation delays  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC3G16DP  
-40 °C to +125 °C  
TSSOP8  
plastic thin shrink small outline package; 8 leads;  
body width 3 mm; lead length 0.5 mm  
SOT505-2  
4. Marking  
Table 2. Marking  
Type number  
Marking code [1]  
74HC3G16DP  
P6  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
 
 
 
 
 

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