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74HC3G34DP PDF预览

74HC3G34DP

更新时间: 2024-11-30 11:11:39
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
13页 191K
描述
Triple buffer gateProduction

74HC3G34DP 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:N系列:HC/UH
JESD-30 代码:S-PDSO-G8JESD-609代码:e4
长度:3 mm逻辑集成电路类型:BUFFER
湿度敏感等级:1功能数量:3
输入次数:1端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):125 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mmBase Number Matches:1

74HC3G34DP 数据手册

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74HC3G34; 74HCT3G34  
Triple buffer gate  
Rev. 7 — 11 June 2018  
Product data sheet  
1 General description  
The 74HC3G34; 74HCT3G34 is a triple buffer. Inputs include clamp diodes. This enables  
the use of current limiting resistors to interface inputs to voltages in excess of VCC  
.
2 Features and benefits  
Wide supply voltage range from 2.0 V to 6.0 V  
Input levels:  
For 74HC3G34: CMOS level  
For 74HCT3G34: TTL level  
Complies with JEDEC standard no. 7 A  
Symmetrical output impedance  
High noise immunity  
Low-power dissipation  
Balanced propagation delays  
Multiple package options  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3 Ordering information  
Table 1.ꢀOrdering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC3G34DP  
74HCT3G34DP  
74HC3G34DC  
74HCT3G34DC  
-40 °C to +125 °C  
TSSOP8  
plastic thin shrink small outline package; 8 leads; SOT505-2  
body width 3 mm; lead length 0.5 mm  
-40 °C to +125 °C  
VSSOP8  
plastic very thin shrink small outline package;  
8 leads; body width 2.3 mm  
SOT765-1  
 
 
 

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