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74HC4002D PDF预览

74HC4002D

更新时间: 2024-11-10 11:14:07
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
11页 217K
描述
Dual 4-input NOR gateProduction

74HC4002D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
逻辑集成电路类型:NOR GATE湿度敏感等级:1
功能数量:2输入次数:4
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):30 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

74HC4002D 数据手册

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74HC4002  
Dual 4-input NOR gate  
Rev. 7 — 13 September 2021  
Product data sheet  
1. General description  
The 74HC4002 is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use of  
current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 V to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
CMOS input levels  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +80 °C and from -40 °C to +125 °C.  
3. Ordering information  
Table 1. Ordering information  
Type number Package  
Temperature range Name  
Description  
Version  
74HC4002D  
-40 °C to +125 °C  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
74HC4002PW -40 °C to +125 °C  
TSSOP14  
plastic thin shrink small outline package; 14 leads;  
body width 4.4 mm  
SOT402-1  
4. Functional diagram  
1A  
2
1A  
2
1B  
3
1Y  
2Y  
1B  
1
1Y  
1C  
4
3
1
1C  
1D  
2A  
2B  
2C  
2D  
1D  
4
5
5
2A  
9
2B  
9
10  
13  
2C  
11  
2Y  
10  
11  
12  
13  
2D  
12  
aaa-004023  
aaa-004024  
Fig. 1. Functional diagram  
Fig. 2. Logic symbol  
 
 
 
 
 

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