Datasheet > 74HC299D-Q100

74HC299D-Q100

更新时间： 2024-10-01 11:10:39

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
15页	249K
描述
8-bit universal shift register; 3-stateProduction

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74HC299D-Q100 数据手册

74HC299-Q100

8-bit universal shift register; 3-state

Rev. 1 — 2 March 2020

Product data sheet

1. General description

The 74HC299-Q100 is an 8-bit universal shift register with 3-state outputs. It contains eight

edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous

shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the

mode select inputs S0 and S1. Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow

them to operate as data inputs in parallel load mode. The serial outputs Q0 and Q7 are used for

expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset

input MR overrides the Sn and clock CP inputs and resets the flip-flops. All other state changes

are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either

state, provided that the recommended set-up and hold times are observed. A HIGH signal on

the 3-state output enable inputs OE1 or OE2 disables the 3-state buffers and the I/On outputs

assume a high-impedance OFF-state. In this condition, the shift, hold, load and reset operations

can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1, when

in preparation for a parallel load operation. Inputs include clamp diodes. This enables the use of

current limiting resistors to interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

CMOS input levels

Multiplexed inputs/outputs provide improved bit density

Four operating modes:

•

Shift left

Shift right

Hold (store)

Load data

•

Operates with output enable or at high-impedance OFF-state

3-state outputs drive bus lines directly

Cascadable for n-bit word lengths

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range

-40 °C to +125 °C

Name

Description

Version

74HC299D-Q100

SO20

plastic small outline package; 20 leads;

body width 7.5 mm

SOT163-1

12 3 4 5 6 7...15

中文翻译

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与74HC299D-Q100相关器件

型号	品牌	获取价格	描述	数据表
74HC299D-T	NXP	获取价格	IC HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT,
74HC299N	NXP	获取价格	8-bit universal shift register; 3-state
74HC299N,652	NXP	获取价格	74HC(T)299 - 8-bit universal shift register; 3-state DIP 20-Pin
74HC299PW	NXP	获取价格	8-bit universal shift register; 3-state
74HC299PW,112	NXP	获取价格	74HC299 - 8-bit universal shift register; 3-state@en-us TSSOP2 20-Pin
74HC299PW,118	NXP	获取价格	74HC299 - 8-bit universal shift register; 3-state@en-us TSSOP2 20-Pin
74HC299PW-T	NXP	获取价格	IC HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT,
74HC2G00	NXP	获取价格	Dual 2-input NAND gate
74HC2G00DC	NEXPERIA	获取价格	Dual 2-input NAND gateProduction
74HC2G00DC	NXP	获取价格	Dual 2-input NAND gate

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