Datasheet > 74HC161-Q100

74HC161-Q100

更新时间： 2024-11-02 01:10:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
17页	272K
描述
Presettable synchronous 4-bit binary counter; asynchronous reset

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74HC161-Q100 数据手册

74HC161-Q100

Presettable synchronous 4-bit binary counter; asynchronous

reset

Rev. 2 — 4 October 2018

Product data sheet

1. General description

The 74HC161-Q100 is a synchronous presettable binary counter with an internal look-head carry.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-

going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW.

A LOW at the parallel enable input (PE) disables the counting action and causes the data at the

data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset

takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master

reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP

(thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading

of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable

the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a

duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next

cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP

to TC propagation delay and CEP to CP set-up time, according to the following formula:

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to

voltages in excess of V_CC

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Complies with JEDEC standard no. 7A

CMOS input levels

Synchronous counting and loading

2 count enable inputs for n-bit cascading

Asynchronous reset

Positive-edge triggered clock

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2 000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

Multiple package options

12 3 4 5 6 7...17

中文翻译

下载PDF

与74HC161-Q100相关器件

型号	品牌	获取价格	描述	数据表
74HC161U	NXP	获取价格	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, UUC, DIE, Counter
74HC162	NXP	获取价格	Presettable synchronous BCD decade counter; synchronous reset
74HC162D-T	ETC	获取价格	Synchronous Up Counter
74HC162N	NXP	获取价格	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16, Counter
74HC162NB	NXP	获取价格	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16, Counter
74HC162PW	NXP	获取价格	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, Counter
74HC163	NXP	获取价格	Presettable synchronous 4-bit binary counter; synchronous reset
74HC163D	NXP	获取价格	Presettable synchronous 4-bit binary counter; synchronous reset
74HC163DB	NXP	获取价格	Presettable synchronous 4-bit binary counter; synchronous reset
74HC163DB-T	NXP	获取价格	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, SOT-338-1, S

与74HC161-Q100相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

4
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

2
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

23
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

24

产品中心

服务支持

精选活动

关于我们

帮助中心

74HC161-Q100

74HC161-Q100 数据手册

与74HC161-Q100相关器件

与74HC161-Q100相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74HC161-Q100

74HC161-Q100 数据手册

与74HC161-Q100相关器件

与74HC161-Q100相关文章

您还可以找

您在本页遇到什么问题？