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74HC00DR2G PDF预览

74HC00DR2G

更新时间: 2024-11-24 06:31:51
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
7页 105K
描述
Quad 2-Input NAND Gate High-Performance Silicon-Gate CMOS

74HC00DR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:6.78
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:22 ns
传播延迟(tpd):110 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mmBase Number Matches:1

74HC00DR2G 数据手册

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74HC00  
Quad 2-Input NAND Gate  
High-Performance Silicon-Gate CMOS  
The 74HC00 is identical in pinout to the LS00. The device inputs are  
compatible with Standard CMOS outputs; with pullup resistors, they  
are compatible with LSTTL outputs.  
http://onsemi.com  
Features  
MARKING  
DIAGRAMS  
ꢀOutput Drive Capability: 10 LSTTL Loads  
ꢀOutputs Directly Interface to CMOS, NMOS and TTL  
ꢀOperating Voltage Range: 2.0 to 6.0 V  
ꢀLow Input Current: 1.0 mA  
14  
SOIC-14  
D SUFFIX  
CASE 751A  
ꢀHigh Noise Immunity Characteristic of CMOS Devices  
ꢀIn Compliance With the JEDEC Standard No. 7A Requirements  
ꢀESD Performance: HBM > 2000 V; Machine Model > 200 V  
ꢀChip Complexity: 32 FETs or 8 Equivalent Gates  
ꢀThese are Pb-Free Devices  
HC00G  
AWLYWW  
14  
1
1
14  
LOGIC DIAGRAM  
HC  
00  
ALYWꢀ  
TSSOP-14  
DT SUFFIX  
CASE 948G  
1
A1  
3
14  
Y1  
2
B1  
1
1
4
A2  
6
Y2  
5
HC00  
A
= Device Code  
= Assembly Location  
B2  
Y = AB  
9
WL or L = Wafer Lot  
= Year  
WW or W = Work Week  
G or = Pb-Free Package  
A3  
8
Y
Y3  
10  
B3  
12  
A4  
(Note: Microdot may be in either location)  
11  
Y4  
13  
B4  
PIN 14 = V  
CC  
PIN 7 = GND  
FUNCTION TABLE  
Pinout: 14-Lead Packages (Top View)  
Inputs  
Output  
Y
V
CC  
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
A
B
14  
L
L
L
H
L
H
H
H
L
H
H
H
1
2
3
4
5
6
7
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
©ꢀ Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
74HC00/D  
March, 2007 - Rev. 1  

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