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MC74HC00ADG PDF预览

MC74HC00ADG

更新时间: 2024-01-23 17:03:21
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 75K
描述
Quad 2-Input NAND Gate

MC74HC00ADG 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
风险等级:5.69JESD-30 代码:R-PDIP-T14
JESD-609代码:e0逻辑集成电路类型:NAND GATE
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V认证状态:Not Qualified
施密特触发器:NO子类别:Gates
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC74HC00ADG 数据手册

 浏览型号MC74HC00ADG的Datasheet PDF文件第2页浏览型号MC74HC00ADG的Datasheet PDF文件第3页浏览型号MC74HC00ADG的Datasheet PDF文件第4页浏览型号MC74HC00ADG的Datasheet PDF文件第5页浏览型号MC74HC00ADG的Datasheet PDF文件第6页 
MC74HC00A  
Quad 2−Input NAND Gate  
High−Performance Silicon−Gate CMOS  
The MC74HC00A is identical in pinout to the LS00. The device  
inputs are compatible with Standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
http://onsemi.com  
Features  
MARKING  
DIAGRAMS  
14  
Pb−Free Packages are Available*  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6 V  
PDIP−14  
N SUFFIX  
CASE 646  
MC74HC00AN  
AWLYYWW  
Low Input Current: 1 mA  
1
14  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7 A Requirements  
Chip Complexity: 32 FETs or 8 Equivalent Gates  
SOIC−14  
D SUFFIX  
CASE 751A  
HC00A  
AWLYWW  
1
14  
LOGIC DIAGRAM  
HC  
00A  
ALYW  
TSSOP−14  
DT SUFFIX  
CASE 948G  
1
A1  
3
Y1  
2
B1  
4
1
A2  
6
A
= Assembly Location  
Y2  
5
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
B2  
Y = AB  
9
A3  
8
Y3  
10  
B3  
12  
FUNCTION TABLE  
A4  
11  
Inputs  
Output  
Y4  
13  
B4  
A
B
Y
PIN 14 = V  
CC  
PIN 7 = GND  
L
L
L
H
L
H
H
H
L
H
H
Pinout: 14−Lead Packages (Top View)  
H
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
14  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
1
2
3
4
5
6
7
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
December, 2004 − Rev. 9  
MC74HC00A/D  

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