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74CBTLV3251RGYRG4 PDF预览

74CBTLV3251RGYRG4

更新时间: 2024-02-22 19:41:10
品牌 Logo 应用领域
德州仪器 - TI 解复用器逻辑集成电路
页数 文件大小 规格书
12页 378K
描述
LOW-VOLTAGE 1-OF-8 FET MULTIPLEXER/DEMULTIPLEXER

74CBTLV3251RGYRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC16/20,.14X.16,20针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.57Is Samacsys:N
系列:CBTLV/3BJESD-30 代码:R-PQCC-N16
JESD-609代码:e4长度:4 mm
逻辑集成电路类型:MULTIPLEXER AND DEMUX/DECODER湿度敏感等级:2
功能数量:1输入次数:1
输出次数:8端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC16/20,.14X.16,20封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5/3.3 V传播延迟(tpd):0.25 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:Other Logic ICs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.5 mmBase Number Matches:1

74CBTLV3251RGYRG4 数据手册

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ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ  
ꢇꢍ ꢎꢏꢈꢍ ꢇꢆꢐꢑ ꢒ ꢌ ꢏꢍ ꢓꢏ ꢔ ꢓ ꢒꢆ ꢕ ꢖꢇꢆ ꢗꢘ ꢇꢒ ꢙꢒꢚꢛ ꢜꢒꢕ ꢖꢇꢆꢗ ꢘ ꢇꢒ ꢙꢒ ꢚ  
SCDS054I − MARCH 1998 − REVISED OCTOBER 2003  
D
D
D
5-Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
D
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
I
Supports Partial-Power-Down Mode  
off  
Operation  
D, DBQ, DGV, OR PW PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
V
B4  
B3  
B2  
B1  
A
NC  
OE  
GND  
1
2
3
4
5
6
7
8
16  
CC  
15 B5  
14 B6  
13 B7  
12 B8  
1
16  
B3  
B2  
B1  
A
NC  
OE  
15  
14  
13  
12  
11  
10  
2
3
4
5
6
7
B5  
B6  
B7  
B8  
S0  
S1  
11  
10  
9
S0  
S1  
S2  
8
9
NC − No internal connection  
NC − No internal connection  
description/ordering information  
The SN74CBTLV3251 device is a 1-of-8 high-speed FET multiplexer/demultiplexer. The low on-state resistance  
of the switch allows connections to be made with minimal propagation delay.  
The select inputs (S0, S1, S2) control the data flow. The FET multiplexers/demultiplexers are disabled when  
the output-enable (OE) input is high.  
This device is fully specified for partial-power-down applications using I . The I feature ensures that  
off  
off  
damaging current will not backflow through the device when it is powered down. The device has isolation during  
power off.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Tape and reel  
SN74CBTLV3251RGYR  
SN74CBTLV3251D  
CL251  
Tube  
CBTLV3251  
Tape and reel  
SN74CBTLV3251DR  
SN74CBTLV3251DBQR  
SN74CBTLV3251PWR  
SN74CBTLV3251DGVR  
−40°C to 85°C  
SSOP (QSOP) − DBQ Tape and reel  
CL251  
CL251  
CL251  
TSSOP − PW  
TVSOP − DGV  
Tape and reel  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢨ  
Copyright 2003, Texas Instruments Incorporated  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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