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74CBTLV3253BQ PDF预览

74CBTLV3253BQ

更新时间: 2024-12-01 11:11:11
品牌 Logo 应用领域
安世 - NEXPERIA 逻辑集成电路
页数 文件大小 规格书
18页 321K
描述
Dual 1-of-4 multiplexer/demultiplexerProduction

74CBTLV3253BQ 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
系列:CBTLV/3BJESD-30 代码:R-PQCC-N16
JESD-609代码:e4长度:3.5 mm
逻辑集成电路类型:MULTIPLEXER AND DEMUX/DECODER湿度敏感等级:1
功能数量:2输入次数:1
输出次数:4端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):0.25 ns
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:2.5 mm
Base Number Matches:1

74CBTLV3253BQ 数据手册

 浏览型号74CBTLV3253BQ的Datasheet PDF文件第2页浏览型号74CBTLV3253BQ的Datasheet PDF文件第3页浏览型号74CBTLV3253BQ的Datasheet PDF文件第4页浏览型号74CBTLV3253BQ的Datasheet PDF文件第5页浏览型号74CBTLV3253BQ的Datasheet PDF文件第6页浏览型号74CBTLV3253BQ的Datasheet PDF文件第7页 
74CBTLV3253  
Dual 1-of-4 multiplexer/demultiplexer  
Rev. 6 — 24 September 2020  
Product data sheet  
1. General description  
The 74CBTLV3253 provides a dual 1-of-4 high-speed multiplexer/demultiplexer with two common  
select inputs (S0, S1) and two output enable inputs (1OE, 2OE). The low ON resistance of the  
switch allows inputs to be connected to outputs without adding propagation delay or generating  
additional ground bounce noise. When pin nOE = LOW, one of the four switches is selected  
(low-impedance ON-state) with pins S0 and S1. When pin nOE = HIGH, all switches are in the  
high-impedance OFF-state, independent of pins S0 and S1.  
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied  
to the VCC through a pull-up resistor. The minimum value of the resistor is determined by the  
current-sinking capability of the driver.  
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times  
across the entire VCC range from 2.3 V to 3.6 V.  
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing the damaging backflow current through the device when it is  
powered down.  
2. Features and benefits  
Supply voltage range from 2.3 V to 3.6 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM AEC-Q100-011 revision B exceeds 1000 V  
5 Ω switch connection between two ports  
Rail to rail switching on data I/O ports  
CMOS low power consumption  
Latch-up performance exceeds 250 mA per JESD78B Class I level A  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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