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74CBTLV3125 PDF预览

74CBTLV3125

更新时间: 2024-11-10 01:09:11
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
17页 291K
描述
4-bit bus switch

74CBTLV3125 数据手册

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74CBTLV3125  
4-bit bus switch  
Rev. 5 — 8 October 2018  
Product data sheet  
1. General description  
The 74CBTLV3125 provides a 4-bit high-speed bus switch with separate output enable inputs (1OE  
to 4OE). The low on-state resistance of the switch allows connections to be made with minimal  
propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable  
(nOE) input is HIGH.  
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to  
the VCC through a pull-up resistor. The minimum value of the resistor is determined by the current-  
sinking capability of the driver.  
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times  
across the entire VCC range from 2.3 V to 3.6 V.  
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing the damaging backflow current through the device when it is  
powered down.  
2. Features and benefits  
Supply voltage range from 2.3 V to 3.6 V  
Standard ’125’-type pinout  
High noise immunity  
Complies with JEDEC standard:  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM AEC-Q100-011 revision B exceeds 1000 V  
5 Ω switch connection between two ports  
Rail to rail switching on data I/O ports  
CMOS low power consumption  
Latch-up performance exceeds 250 mA per JESD78B Class I level A  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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