ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ
ꢒ
ꢇ
ꢍ
ꢎ
ꢏ
ꢈ
ꢍ
ꢇ
ꢆ
ꢐ
ꢑ
ꢒ
ꢓ
ꢔ
ꢐ
ꢕ
ꢖ
ꢔ
ꢗ
ꢇ
ꢒ
ꢘ
ꢆ
ꢅ
ꢔ
ꢀ
ꢀ
ꢎ
ꢙ
ꢆ
ꢄ
ꢚ
SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003
D
D
D
Standard ’126-Type Pinout
D
D
I
Supports Partial-Power-Down Mode
off
Operation
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
Latch-up Performance Exceeds 100 mA per
JESD 78, Class II
D, DGV, OR PW PACKAGE
DBQ PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1OE
1A
1B
2OE
2A
2B
V
CC
4OE
V
NC
1OE
1A
1B
2OE
2A
1
2
3
4
5
6
7
8
16
CC
15 4OE
14 4A
1
14
4A
4B
3OE
3A
3B
1A
1B
13 4OE
12 4A
2
3
4
5
6
13 4B
12 3OE
11
10
9
2OE
2A
4B
11
10
9
3A
3B
NC
3OE
3A
8
GND
2B
GND
2B
7
8
NC − No internal connection
description/ordering information
The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled
when the associated output-enable (OE) input is low.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − D
Tape and reel
SN74CBTLV3126RGYR
SN74CBTLV3126D
CL126
Tube
CBTLV3126
Tape and reel
SN74CBTLV3126DR
SN74CBTLV3126DBQR
SN74CBTLV3126PWR
SN74CBTLV3126DGVR
−40°C to 85°C
SSOP (QSOP) − DBQ Tape and reel
CL126
CL126
CL126
TSSOP − PW
TVSOP − DGV
Tape and reel
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each bus switch)
INPUT
FUNCTION
OE
L
Disconnect
H
A port = B port
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢗ
ꢖ
ꢍ
ꢕ
ꢔ
ꢄ
ꢆ
ꢙ
ꢍ
ꢁ
ꢕ
ꢐ
ꢆ
ꢐ
ꢛ
ꢜ
ꢝ
ꢞ
ꢟ
ꢠ
ꢡ
ꢢ
ꢛ
ꢞ
ꢜ
ꢛ
ꢣ
ꢤ
ꢥ
ꢟ
ꢟ
ꢦ
ꢜ
ꢢ
ꢡ
ꢣ
ꢞ
ꢝ
ꢧ
ꢥ
ꢨ
ꢩ
ꢛ
ꢤ
ꢡ
ꢢ
ꢛ
ꢞ
ꢜ
ꢪ
ꢡ
ꢢ
ꢦ
ꢫ
Copyright 2003, Texas Instruments Incorporated
ꢗꢟ ꢞ ꢪꢥꢤ ꢢ ꢣ ꢤ ꢞꢜ ꢝꢞ ꢟ ꢠ ꢢ ꢞ ꢣ ꢧꢦ ꢤ ꢛꢝ ꢛꢤꢡ ꢢꢛ ꢞꢜꢣ ꢧꢦ ꢟ ꢢꢬ ꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢆꢦꢭ ꢡꢣ ꢙꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ
ꢣ ꢢ ꢡ ꢜꢪ ꢡ ꢟꢪ ꢮ ꢡ ꢟꢟ ꢡ ꢜ ꢢꢯꢫ ꢗꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞꢜ ꢧꢟ ꢞꢤ ꢦꢣ ꢣꢛ ꢜꢰ ꢪꢞꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265