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74AVC16T245DGG PDF预览

74AVC16T245DGG

更新时间: 2024-11-26 11:13:27
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
22页 306K
描述
16-bit dual supply translating transceiver with configurable voltage translation; 3-stateProduction

74AVC16T245DGG 数据手册

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74AVC16T245  
16-bit dual supply translating transceiver with configurable  
voltage translation; 3-state  
Rev. 7 — 14 January 2019  
Product data sheet  
1. General description  
The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state  
outputs. The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual  
supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and  
nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control.  
VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making  
the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V,  
1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW  
on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a  
high-impedance OFF-state  
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing any damaging backflow current through the device when it is  
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn  
are in the high-impedance OFF-state.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101D exceeds 1000 V  
Maximum data rates:  
380 Mbit/s (≥ 1.8 V to 3.3 V translation)  
200 Mbit/s (≥ 1.1 V to 3.3 V translation)  
200 Mbit/s (≥ 1.1 V to 2.5 V translation)  
200 Mbit/s (≥ 1.1 V to 1.8 V translation)  
150 Mbit/s (≥ 1.1 V to 1.5 V translation)  
100 Mbit/s (≥ 1.1 V to 1.2 V translation)  
Suspend mode  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
IOFF circuitry provides partial Power-down mode operation  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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