Datasheet > 74AUP1G32GS,132

74AUP1G32GS,132

更新时间： 2024-02-21 09:43:14

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
21页	347K
描述
74AUP1G32 - Low-power 2-input OR-gate

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技术参数
数据手册

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74AUP1G32GS,132 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	包装说明：	1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, SON-6
Reach Compliance Code：	compliant	风险等级：	5.76
Base Number Matches：	1

74AUP1G32GS,132 数据手册

74AUP1G32

NXP Semiconductors

Low-power 2-input OR-gate

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74AUP1G32GW

74AUP1G32GM

74AUP1G32GF

74AUP1G32GN

74AUP1G32GS

74AUP1G32GX

40 C to +125 C

TSSOP5

plastic thin shrink small outline package; 5 leads;

body width 1.25 mm

SOT353-1

XSON6

X2SON5

plastic extremely thin small outline package; no leads; SOT886

6 terminals; body 1  1.45  0.5 mm

plastic extremely thin small outline package; no leads; SOT891

6 terminals; body 1  1  0.5 mm

extremely thin small outline package; no leads;

6 terminals; body 0.9  1.0  0.35 mm

SOT1115

SOT1202

SOT1226

extremely thin small outline package; no leads;

6 terminals; body 1.0  1.0  0.35 mm

X2SON5: plastic thermal enhanced extremely thin

small outline package; no leads; 5 terminals;

body 0.8  0.8  0.35 mm

4. Marking

Table 2.

Marking

Type number

Marking code^[1]

74AUP1G32GW

74AUP1G32GM

74AUP1G32GF

74AUP1G32GN

74AUP1G32GS

74AUP1G32GX

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

≥1

mna166

mna165

mna164

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram

74AUP1G32

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 8 July 2013

2 of 21

123 4 5 6 7...21

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