Datasheet > 74AUP1G32GS,132

74AUP1G32GS,132

更新时间： 2024-02-16 00:41:23

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
21页	347K
描述
74AUP1G32 - Low-power 2-input OR-gate

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技术参数
数据手册

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74AUP1G32GS,132 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	包装说明：	1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, SON-6
Reach Compliance Code：	compliant	风险等级：	5.76
Base Number Matches：	1

74AUP1G32GS,132 数据手册

74AUP1G32

NXP Semiconductors

Low-power 2-input OR-gate

14. Abbreviations

Table 12. Abbreviations

Acronym

CDM

DUT

Description

Charged Device Model

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

ESD

HBM

15. Revision history

Table 13. Revision history

Document ID

74AUP1G32 v.7

Modifications:

74AUP1G32 v.6

Modifications:

74AUP1G32 v.5

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20130708

Product data sheet

74AUP1G32 v.6

• Descriptive product title on page 1 change to Low-power 2-input OR-gate

20130705

• Typical values C_Iand C_Ocorrected (errata).

20120628 Product data sheet

• Added type number 74AUP1G32GX (SOT1226)

• Package outline drawing of SOT886 (Figure 11) modified.

Product data sheet

74AUP1G32 v.5

74AUP1G32 v.4

Modifications:

20111123

Product data sheet

74AUP1G32 v.3

• Legal pages updated.

74AUP1G32 v.3

74AUP1G32 v.2

74AUP1G32 v.1

20101012

20060721

20050802

Product data sheet

74AUP1G32 v.2

Product data sheet

74AUP1G32 v.1

74AUP1G32

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 8 July 2013

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1...15 16 171819 20 21

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