5秒后页面跳转
捷配首页

Datasheet > 74ALVCH16601DGVRG4
74ALVCH16601DGVRG4 PDF预览

74ALVCH16601DGVRG4

更新时间： 2024-11-06 14:40:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路电视
页数 文件大小 规格书
15页 358K
描述
ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TVSOP-56

阅读下载

中文翻译

获取价格

74ALVCH16601DGVRG4 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：compliant风险等级：5.84
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：11.3 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
湿度敏感等级：1位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：5.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

74ALVCH16601DGVRG4 数据手册

 浏览型号74ALVCH16601DGVRG4的Datasheet PDF文件第2页浏览型号74ALVCH16601DGVRG4的Datasheet PDF文件第3页浏览型号74ALVCH16601DGVRG4的Datasheet PDF文件第4页浏览型号74ALVCH16601DGVRG4的Datasheet PDF文件第5页浏览型号74ALVCH16601DGVRG4的Datasheet PDF文件第6页浏览型号74ALVCH16601DGVRG4的Datasheet PDF文件第7页 
SN74ALVCH16601  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES027F–JULY 1995–REVISED OCTOBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A1  
GND  
A2  
CLKENAB  
CLKAB  
B1  
GND  
B2  
•
UBT™ (Universal Bus Transceiver) Combines  
D-Type Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, Clocked,  
or Clock-Enabled Modes  
2
3
4
5
•
•
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
6
A3  
B3  
7
V
CC  
V
CC  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
8
A4  
A5  
A6  
GND  
A7  
A8  
B4  
B5  
B6  
GND  
B7  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
B8  
A9  
B9  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
DESCRIPTION  
This 18-bit universal bus transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
The SN74ALVCH16601 combines D-type latches and  
D-type flip-flops to allow data flow in transparent,  
latched, and clocked modes.  
A16  
A17  
B16  
B17  
GND  
A18  
OEBA  
LEBA  
GND  
B18  
CLKBA  
CLKENBA  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and CLKBA)  
inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs. For  
A-to-B data flow, the device operates in the  
transparent mode when LEAB is high. When LEAB is  
low, the A data is latched if CLKAB is held at a high  
or low logic level. If LEAB is low, the A data is stored  
in the latch/flip-flop on the low-to-high transition of  
CLKAB. Output enable OEAB is active low. When  
OEAB is low, the outputs are active. When OEAB is  
high, the outputs are in the high-impedance state.  
<br/>  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16601 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

中文翻译

下载PDF

与74ALVCH16601DGVRG4相关器件

型号 品牌 获取价格 描述 数据表
74ALVCH16601DL PHILIPS

获取价格

 		Registered Bus Transceiver, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
74ALVCH16601DLG4 TI

获取价格

 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN,
74ALVCH16601DLRG4 TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
74ALVCH16601DL-T NXP

获取价格

 		IC ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Trans
74ALVCH16623 NXP

获取价格

 		16-bit transceiver with dual enable; 3-state
74ALVCH16623DG NXP

获取价格

 		暂无描述
74ALVCH16623DGG NXP

获取价格

 		16-bit transceiver with dual enable; 3-state
74ALVCH16623DGG,51 NXP

获取价格

 		74ALVCH16623DGG
74ALVCH16623DGG:51 NXP

获取价格

 		暂无描述
74ALVCH16623DGG-T NXP

获取价格

 		IC ALVC/VCX/A SERIES, 16-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-362, TSSOP-48,

与74ALVCH16601DGVRG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证