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74ALVCH16601DGGRG4 PDF预览

74ALVCH16601DGGRG4

更新时间： 2024-11-10 01:11:19
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德州仪器 - TI 输出元件
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15页 374K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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74ALVCH16601DGGRG4 数据手册

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SN74ALVCH16601  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES027F–JULY 1995–REVISED OCTOBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
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56  
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29  
OEAB  
LEAB  
A1  
GND  
A2  
CLKENAB  
CLKAB  
B1  
GND  
B2  
•
UBT™ (Universal Bus Transceiver) Combines  
D-Type Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, Clocked,  
or Clock-Enabled Modes  
2
3
4
5
•
•
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
6
A3  
B3  
7
V
CC  
V
CC  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
8
A4  
A5  
A6  
GND  
A7  
A8  
B4  
B5  
B6  
GND  
B7  
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10  
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12  
13  
14  
15  
16  
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18  
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•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
B8  
A9  
B9  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
DESCRIPTION  
This 18-bit universal bus transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
The SN74ALVCH16601 combines D-type latches and  
D-type flip-flops to allow data flow in transparent,  
latched, and clocked modes.  
A16  
A17  
B16  
B17  
GND  
A18  
OEBA  
LEBA  
GND  
B18  
CLKBA  
CLKENBA  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and CLKBA)  
inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs. For  
A-to-B data flow, the device operates in the  
transparent mode when LEAB is high. When LEAB is  
low, the A data is latched if CLKAB is held at a high  
or low logic level. If LEAB is low, the A data is stored  
in the latch/flip-flop on the low-to-high transition of  
CLKAB. Output enable OEAB is active low. When  
OEAB is low, the outputs are active. When OEAB is  
high, the outputs are in the high-impedance state.  
<br/>  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16601 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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74ALVCH16601DGGRG4 替代型号

型号 品牌 替代类型 描述 数据表
74ALVCH16601DGGRE4 TI

完全替代

 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16601DGGR TI

完全替代

 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16601DGG TI

功能相似

 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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