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74ALVCH16245DGG PDF预览

74ALVCH16245DGG

更新时间: 2024-11-06 11:15:35
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
13页 227K
描述
16-bit transceiver with direction pin; 3-stateProduction

74ALVCH16245DGG 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP-48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.05
Is Samacsys:N其他特性:WITH DIRECTION CONTROL
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:12.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS TRANSCEIVER
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):3.7 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:6.1 mmBase Number Matches:1

74ALVCH16245DGG 数据手册

 浏览型号74ALVCH16245DGG的Datasheet PDF文件第2页浏览型号74ALVCH16245DGG的Datasheet PDF文件第3页浏览型号74ALVCH16245DGG的Datasheet PDF文件第4页浏览型号74ALVCH16245DGG的Datasheet PDF文件第5页浏览型号74ALVCH16245DGG的Datasheet PDF文件第6页浏览型号74ALVCH16245DGG的Datasheet PDF文件第7页 
74ALVC16245; 74ALVCH16245  
16-bit transceiver with direction pin; 3-state  
Rev. 6 — 5 August 2021  
Product data sheet  
1. General description  
The 74ALVC16245; 74ALVCH16245 is a 16-bit transceiver with 3-state outputs. The device can be  
used as two 8-bit transceivers or one 16-bit transceiver. The device features two output enables  
(1OE and 2OE) each controlling eight outputs, and two send/receive (1DIR and 2DIR) inputs for  
direction control. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. This  
device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables  
the output, preventing the potentially damaging backflow current through the device when it is  
powered down.  
The 74ALVCH16245 has an active bushold circuitry which is provided to hold unused or floating  
data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down  
resistors.  
2. Features and benefits  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
MULTIBYTE flow-through standard pin-out architecture  
Low inductance multiple VCC and GND pins for minimize noise and ground bounce  
Overvoltage tolerant inputs to 5.5 V  
Direct interface with TTL levels  
IOFF circuitry provides partial Power-down mode operation  
All data inputs have bushold (74ALVCH16245 only)  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Output drive capability 50 Ω transmission lines at 85 °C  
Current drive ±24 mA at VCC = 3.0 V.  
Complies with JEDEC standards:  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V  
CDM JESD22-C101E exceeds 1000 V  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74ALVC16245DGG  
74ALVCH16245DGG  
-40 °C to +85 °C  
TSSOP48  
plastic thin shrink small outline package;  
48 leads; body width 6.1 mm  
SOT362-1  
 
 
 

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