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74ALVCH16245DLRG4 PDF预览

74ALVCH16245DLRG4

更新时间： 2024-11-21 05:05:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
17页 465K
描述
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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中文翻译

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74ALVCH16245DLRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：GREEN, PLASTIC, SSOP-48针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.08Is Samacsys：N
其他特性：WITH DIRECTION CONTROL系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：15.875 mm逻辑集成电路类型：BUS TRANSCEIVER
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：3.7 ns认证状态：Not Qualified
座面最大高度：2.79 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.49 mmBase Number Matches：1

74ALVCH16245DLRG4 数据手册

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SN74ALVCH16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES015L–JULY 1995–REVISED NOVEMBER 2005  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
48  
47  
46  
45  
44  
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42  
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35  
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33  
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31  
30  
29  
28  
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26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 3 ns at 3.3 V  
2
3
±24-mA Output Drive at 3.3 V  
4
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
5
6
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
9
10  
11  
12  
13  
14  
15  
16  
17  
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DESCRIPTION/ORDERING INFORMATION  
This 16-bit (dual-octal) noninverting bus transceiver is  
designed for 1.65-V to 3.6-V VCC operation.  
The  
SN74ALVCH16245  
is  
designed  
for  
asynchronous communication between two data  
buses. The logic levels of the direction-control (DIR)  
input and the output-enable (OE) input activate either  
the B-port outputs or the A-port outputs or place both  
output ports into the high-impedance mode. The  
device transmits data from the A bus to the B bus  
when the B-port outputs are activated, and from the B  
bus to the A bus when the A-port outputs are  
activated. The input circuitry on both A and B ports is  
always active and must have a logic HIGH or LOW  
V
CC  
V
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2DIR  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
level applied to prevent excess ICC and ICCZ  
.
xxxxxx  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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