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74ALVC164245DL,118 PDF预览

74ALVC164245DL,118

更新时间: 2024-11-23 21:14:11
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
19页 103K
描述
74ALVC164245 - 16-bit dual supply translating transceiver; 3-state SSOP 48-Pin

74ALVC164245DL,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SSOP包装说明:7.50 MM, PLASTIC, MO-118, SOT-370-1, SSOP-48
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.32
其他特性:PORT A IS OPERATED AT VOLTAGE 1.5-3.6V控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G48长度:15.875 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3,5 V
Prop。Delay @ Nom-Sup:7.5 ns传播延迟(tpd):9.5 ns
认证状态:Not Qualified座面最大高度:2.8 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.5 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL/PALLADIUM/GOLD (NI/PD/AU)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
翻译:3V & 5V宽度:7.5 mm
Base Number Matches:1

74ALVC164245DL,118 数据手册

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74ALVC164245  
16-bit dual supply translating transceiver; 3-state  
Rev. 04 — 11 November 2008  
Product data sheet  
1. General description  
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS  
device, superior to most advanced CMOS compatible TTL families.  
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring  
non-inverting 3-state bus compatible outputs in both send and receive directions. It is  
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply  
environment.  
This device can be used as two 8-bit transceivers or one 16-bit transceiver.  
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.  
nDIR (active HIGH) enables data from nA ports to nB ports. nDIR (active LOW) enables  
data from nB ports to nA ports. The output enable inputs (1OE and 2OE), when HIGH,  
disable both nA and nB ports by placing them in a high-impedance OFF-state. Pins nA,  
nOE and nDIR are referenced to VCC(A) and pins nB are referenced to VCC(B)  
.
In suspend mode, when one of the supply voltages is zero, there will be no current flow  
from the non-zero supply towards the zero supply. The A-outputs must be set 3-state and  
the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) VCC(A)  
(except in suspend mode).  
2. Features  
I 5 V tolerant inputs/outputs for interfacing with 5 V logic  
I Wide supply voltage range:  
N 3 V port (VCC(A)): 1.5 V to 3.6 V  
N 5 V port (VCC(B)): 1.5 V to 5.5 V  
I CMOS low power consumption  
I Direct interface with TTL levels  
I Control inputs voltage range from 2.7 V to 5.5 V  
I Inputs accept voltages up to 5.5 V  
I High-impedance outputs when VCC(A) or VCC(B) = 0 V  
I Complies with JEDEC standard JESD8-B/JESD36  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Specified from 40 °C to +85 °C and 40 °C to +125 °C  
 
 

74ALVC164245DL,118 替代型号

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