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74ALVC16500MTDX PDF预览

74ALVC16500MTDX

更新时间： 2024-09-13 23:24:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 88K
描述
18-Bit Bus Transceiver

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74ALVC16500MTDX 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：6.1 MM, MO-153, TSSOP-56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.83Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e3长度：14 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.024 A
湿度敏感等级：2位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：3.4 ns
传播延迟（tpd）：9.8 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：NEGATIVE EDGE宽度：6.1 mm
Base Number Matches：1

74ALVC16500MTDX 数据手册

 浏览型号74ALVC16500MTDX的Datasheet PDF文件第2页浏览型号74ALVC16500MTDX的Datasheet PDF文件第3页浏览型号74ALVC16500MTDX的Datasheet PDF文件第4页浏览型号74ALVC16500MTDX的Datasheet PDF文件第5页浏览型号74ALVC16500MTDX的Datasheet PDF文件第6页浏览型号74ALVC16500MTDX的Datasheet PDF文件第7页 
October 2001  
Revised October 2001  
74ALVC16500  
Low Voltage 18-Bit Universal Bus Transceivers  
with 3.6V Tolerant Inputs and Outputs  
General Description  
The ALVC16500 is an 18-bit universal bus transceiver  
which combines D-type latches and D-type flip-flops to  
allow data flow in transparent, latched, and clocked modes.  
Features  
■ 1.65V–3.6V VCC supply operation  
■ 3.6V tolerant inputs and outputs  
■ tPD (A to B, B to A)  
Data flow in each direction is controlled by output-enable  
(OEAB and OEBA), latch-enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the  
device operates in the transparent mode when LEAB is  
HIGH. When LEAB is LOW, the A data is latched if CLKAB  
is held at a HIGH or LOW logic level. If LEAB is LOW, the A  
bus data is stored in the latch/flip-flop on the HIGH-to-LOW  
transition of CLKAB. When OEAB is HIGH, the outputs are  
active. When OEAB is LOW, the outputs are in a high-  
impedance state.  
3.4 ns max for 3.0V to 3.6V VCC  
4.0 ns max for 2.3V to 2.7V VCC  
7.0 ns max for 1.65V to 1.95V VCC  
■ Power-off high impedance inputs and outputs  
■ Supports live insertion/withdrawal (Note 1)  
■ Uses patented noise/EMI reduction circuitry  
■ Latchup conforms to JEDEC JED78  
■ ESD performance:  
Data flow for B to A is similar to that of A to B but uses  
OEBA, LEBA, and CLKBA. The output enables are com-  
plementary (OEAB is active HIGH and OEBA is active  
LOW).  
Human body model > 2000V  
Machine model >200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OEBA should be tied to VCC through a pull-up resistor and OEAB  
The ALVC16500 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O capability up to 3.6V.  
should be tied to GND through a pull-down resistors; the minimum value of  
the resistor is determined by the current-sourcing capability of the driver.  
The 74ALVC16500 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74ALVC16500MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2001 Fairchild Semiconductor Corporation  
DS500684  
www.fairchildsemi.com  
1234567

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