5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> 74ALVC16500MTD
74ALVC16500MTD PDF预览

74ALVC16500MTD

更新时间： 2024-11-22 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 88K
描述
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

阅读下载

中文翻译

获取价格

74ALVC16500MTD 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, MO-153, TSSOP-56
针数：56Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.3
Is Samacsys：N控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e3
长度：14 mm逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.024 A湿度敏感等级：2
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：3.4 ns
传播延迟（tpd）：9.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：NEGATIVE EDGE宽度：6.1 mm
Base Number Matches：1

74ALVC16500MTD 数据手册

 浏览型号74ALVC16500MTD的Datasheet PDF文件第2页浏览型号74ALVC16500MTD的Datasheet PDF文件第3页浏览型号74ALVC16500MTD的Datasheet PDF文件第4页浏览型号74ALVC16500MTD的Datasheet PDF文件第5页浏览型号74ALVC16500MTD的Datasheet PDF文件第6页浏览型号74ALVC16500MTD的Datasheet PDF文件第7页 
October 2001  
Revised October 2001  
74ALVC16500  
Low Voltage 18-Bit Universal Bus Transceivers  
with 3.6V Tolerant Inputs and Outputs  
General Description  
The ALVC16500 is an 18-bit universal bus transceiver  
which combines D-type latches and D-type flip-flops to  
allow data flow in transparent, latched, and clocked modes.  
Features  
■ 1.65V–3.6V VCC supply operation  
■ 3.6V tolerant inputs and outputs  
■ tPD (A to B, B to A)  
Data flow in each direction is controlled by output-enable  
(OEAB and OEBA), latch-enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the  
device operates in the transparent mode when LEAB is  
HIGH. When LEAB is LOW, the A data is latched if CLKAB  
is held at a HIGH or LOW logic level. If LEAB is LOW, the A  
bus data is stored in the latch/flip-flop on the HIGH-to-LOW  
transition of CLKAB. When OEAB is HIGH, the outputs are  
active. When OEAB is LOW, the outputs are in a high-  
impedance state.  
3.4 ns max for 3.0V to 3.6V VCC  
4.0 ns max for 2.3V to 2.7V VCC  
7.0 ns max for 1.65V to 1.95V VCC  
■ Power-off high impedance inputs and outputs  
■ Supports live insertion/withdrawal (Note 1)  
■ Uses patented noise/EMI reduction circuitry  
■ Latchup conforms to JEDEC JED78  
■ ESD performance:  
Data flow for B to A is similar to that of A to B but uses  
OEBA, LEBA, and CLKBA. The output enables are com-  
plementary (OEAB is active HIGH and OEBA is active  
LOW).  
Human body model > 2000V  
Machine model >200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OEBA should be tied to VCC through a pull-up resistor and OEAB  
The ALVC16500 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O capability up to 3.6V.  
should be tied to GND through a pull-down resistors; the minimum value of  
the resistor is determined by the current-sourcing capability of the driver.  
The 74ALVC16500 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74ALVC16500MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2001 Fairchild Semiconductor Corporation  
DS500684  
www.fairchildsemi.com  
1234567

中文翻译

下载PDF

与74ALVC16500MTD相关器件

型号 品牌 获取价格 描述 数据表
74ALVC16500MTDX FAIRCHILD

获取价格

 		18-Bit Bus Transceiver
74ALVC16501 FAIRCHILD

获取价格

 		Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74ALVC16501DGG NXP

获取价格

 		IC ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Trans
74ALVC16501DL NXP

获取价格

 		IC ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Trans
74ALVC16501DL-T NXP

获取价格

 		IC ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Trans
74ALVC16501MTD FAIRCHILD

获取价格

 		Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74ALVC16501MTDX FAIRCHILD

获取价格

 		18-Bit Bus Transceiver
74ALVC16540DGG ETC

获取价格

 		Dual 8-Bit Buffer/Driver
74ALVC16540DGG-T NXP

获取价格

 		IC ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, INVERTED OUTPUT, PDSO48, Bus Driver/Transceiver
74ALVC16540DL NXP

获取价格

 		IC ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, INVERTED OUTPUT, PDSO48, Bus Driver/Transceiver

与74ALVC16500MTD相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证