Datasheet > 74ALS09

74ALS09

更新时间： 2024-09-14 22:36:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
4页	51K
描述
Quad 2-Input AND Gate with Open Collector Outputs

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数据手册

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74ALS09 数据手册

September 1986

Revised February 2000

DM74ALS09

Quad 2-Input AND Gate with Open Collector Outputs

General Description

Features

This device contains four independent gates, each of which

performs the logic AND function. The open-collector out-

puts require external pull-up resistors for proper logical

operation.

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V_CCrange

■ Advanced oxide-isolated, ion-implanted Schottky TTL

process

Pull-Up Resistor Equations

■ Functionally and pin for pin compatible with Schottky

and low power Schottky TTL counterpart

■ Improved AC performance over Schottky and low power

Schottky counterparts

Where:

N₁(I_OH) = total maximum output HIGH current

for all outputs tied to pull-up resistor

N₂(I_IH) = total maximum input HIGH current

for all inputs tied to pull-up resistor

N₃(I_IL) = total maximum input LOW current for

all inputs tied to pull-up resistor

Ordering Code:

Order Number Package Number

Package Description

DM74ALS09M

DM74ALS09N

M14A

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Y = AB

Inputs

Output

H = HIGH Logic Level

L = LOW Logic Level

DS006179

www.fairchildsemi.com

12 3 4

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