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74ALS09 PDF预览

74ALS09

更新时间: 2024-11-03 22:36:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
4页 51K
描述
Quad 2-Input AND Gate with Open Collector Outputs

74ALS09 数据手册

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September 1986  
Revised February 2000  
DM74ALS09  
Quad 2-Input AND Gate with Open Collector Outputs  
General Description  
Features  
This device contains four independent gates, each of which  
performs the logic AND function. The open-collector out-  
puts require external pull-up resistors for proper logical  
operation.  
Switching specifications at 50 pF  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Pull-Up Resistor Equations  
Functionally and pin for pin compatible with Schottky  
and low power Schottky TTL counterpart  
Improved AC performance over Schottky and low power  
Schottky counterparts  
Where:  
N1 (IOH) = total maximum output HIGH current  
for all outputs tied to pull-up resistor  
N2 (IIH) = total maximum input HIGH current  
for all inputs tied to pull-up resistor  
N3 (IIL) = total maximum input LOW current for  
all inputs tied to pull-up resistor  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74ALS09M  
DM74ALS09N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = AB  
Inputs  
Output  
A
L
B
L
Y
L
L
H
L
L
H
H
L
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006179  
www.fairchildsemi.com  

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