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74AHC1G09GW-G PDF预览

74AHC1G09GW-G

更新时间: 2024-11-25 13:04:55
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恩智浦 - NXP /
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74AHC1G09GW-G 数据手册

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74AHC1G09  
2-input AND gate with open-drain output  
Rev. 01 — 26 September 2005  
Product data sheet  
1. General description  
The 74AHC1G09 is a high-speed Si-gate CMOS device.  
The 74AHC1G09 provides the 2-input AND function with open-drain output.  
The output of the 74AHC1G09 is an open drain and can be connected to other open-drain  
outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For  
digital operation this device must have a pull-up resistor to establish a logic HIGH level.  
2. Features  
High noise immunity  
ESD protection:  
HBM JESD22-A114-C exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Low power dissipation  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C.  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.  
Symbol  
Parameter  
Conditions  
Min Typ Max Unit  
tPZL, tPLZ  
propagation delay  
A and B to Y  
VCC = 4.5 V to 5.5 V;  
CL = 15 pF  
-
3.2  
5.5  
ns  
Ci  
input capacitance  
-
-
1.5  
5
10  
-
pF  
pF  
[1]  
CPD  
power dissipation  
capacitance  
CL = 50 pF; fi = 1 MHz;  
VI = GND to VCC  
[1] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts;  
N = number of inputs switching;  
(CL × VCC2 × fo) = dissipation due to the output if the combination of the pull up voltage and resistance  
results in VCC at the output.  

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