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74ACTQ74SCX_NL PDF预览

74ACTQ74SCX_NL

更新时间: 2024-11-02 13:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
8页 217K
描述
D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 0.150 INCH, MS-120, SOIC-14

74ACTQ74SCX_NL 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, MS-120, SOIC-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.68
Is Samacsys:N系列:ACT
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:125000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
传播延迟(tpd):8.6 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:200 MHz
Base Number Matches:1

74ACTQ74SCX_NL 数据手册

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March 1993  
Revised November 1999  
74ACTQ74  
Quiet Series Dual D-Type  
Positive Edge-Triggered Flip-Flop  
Asynchronous Inputs:  
LOW input to SD (Set) sets Q to HIGH level  
General Description  
The 74ACTQ74 is a dual D-type flip-flop with Asynchro-  
nous Clear and Set inputs and complementary (Q, Q) out-  
puts. Information at the input is transferred to the outputs  
on the positive edge of the clock pulse. Clock triggering  
occurs at a voltage level of the clock pulse and is not  
directly related to the transition time of the positive-going  
pulse. After the Clock Pulse input threshold voltage has  
been passed, the Data input is locked out and information  
present will not be transferred to the outputs until the next  
rising edge of the Clock Pulse input.  
LOW input to CD (Clear) sets Q to LOW level  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD makes  
both Q and Q HIGH  
Features  
ICC reduced by 50%  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
The ACTQ74 utilizes Fairchild Quiet Series technology to  
guarantee quiet output switching and improved dynamic  
Guaranteed pin-to-pin skew AC performance  
Improved latch-up immunity  
threshold performance. FACT Quiet Series  
GTO output control and undershoot corrector in addition  
to a split ground bus for superior performance.  
features  
4 kV minimum ESD immunity  
TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACTQ74SC  
74ACTQ74SJ  
74ACTQ74PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
Data Inputs  
D1, D2  
CP1, CP2  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
CD1, CD2  
SD1, SD2  
Q1, Q1, Q2, Q2  
FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010920  
www.fairchildsemi.com  

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