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74ACTQ823CW PDF预览

74ACTQ823CW

更新时间: 2024-11-02 20:56:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动逻辑集成电路
页数 文件大小 规格书
7页 73K
描述
Bus Driver, ACT Series, 1-Func, 9-Bit, True Output, CMOS, DIE

74ACTQ823CW 技术参数

生命周期:Obsolete零件包装代码:DIE
包装说明:DIE,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.74系列:ACT
JESD-30 代码:R-XUUC-N24逻辑集成电路类型:BUS DRIVER
位数:9功能数量:1
端口数量:2端子数量:24
输出特性:3-STATE输出极性:TRUE
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
传播延迟(tpd):9 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS端子形式:NO LEAD
端子位置:UPPERBase Number Matches:1

74ACTQ823CW 数据手册

 浏览型号74ACTQ823CW的Datasheet PDF文件第2页浏览型号74ACTQ823CW的Datasheet PDF文件第3页浏览型号74ACTQ823CW的Datasheet PDF文件第4页浏览型号74ACTQ823CW的Datasheet PDF文件第5页浏览型号74ACTQ823CW的Datasheet PDF文件第6页浏览型号74ACTQ823CW的Datasheet PDF文件第7页 
May 1991  
Revised December 1998  
74ACTQ823  
Quiet Series 9-Bit D-Type Flip-Flop  
with 3-STATE Outputs  
General Description  
Features  
Guaranteed simultaneous switching noise level and  
The ACTQ823 is a 9-bit buffered register. It features Clock  
Enable and Clear which are ideal for parity bus interfacing  
in high performance microprogramming systems. The  
ACTQ823 utilizes Fairchild Quiet Series technology to  
guarantee quiet output switching and improved dynamic  
threshold performance. FACT Quiet Series  
GTO output control and undershoot corrector in addition  
to a split ground bus for superior performance.  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Inputs and outputs on opposite sides of package allow  
easy interface with microprocessors  
features  
Improved latch-up immunity  
Has TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACTQ823SC  
M24B  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide  
74ACTQ823SPC  
N24C  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.  
Logic Symbols  
Connection Diagram  
Pin Assignment  
for DIP and SOIC  
IEEE/IEC  
Pin Descriptions  
Pin Names  
D0–D8  
Description  
Data Inputs  
O0–O8  
OE  
Data Outputs  
Output Enable  
CLR  
CP  
Clear  
Clock Input  
EN  
Clock Enable  
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010921.prf  
www.fairchildsemi.com  

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