74ACTQ74

更新时间： 2024-10-31 22:19:15

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
8页	217K
描述
Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

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中文翻译

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74ACTQ74 数据手册

March 1993

Revised November 1999

74ACTQ74

Quiet Series Dual D-Type

Positive Edge-Triggered Flip-Flop

Asynchronous Inputs:

LOW input to S_D(Set) sets Q to HIGH level

General Description

The 74ACTQ74 is a dual D-type flip-flop with Asynchro-

nous Clear and Set inputs and complementary (Q, Q) out-

puts. Information at the input is transferred to the outputs

on the positive edge of the clock pulse. Clock triggering

occurs at a voltage level of the clock pulse and is not

directly related to the transition time of the positive-going

pulse. After the Clock Pulse input threshold voltage has

been passed, the Data input is locked out and information

present will not be transferred to the outputs until the next

rising edge of the Clock Pulse input.

LOW input to C_D(Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C_Dand S_Dmakes

both Q and Q HIGH

Features

■ I_CCreduced by 50%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

The ACTQ74 utilizes Fairchild Quiet Series technology to

guarantee quiet output switching and improved dynamic

■ Guaranteed pin-to-pin skew AC performance

■ Improved latch-up immunity

threshold performance. FACT Quiet Series

GTO output control and undershoot corrector in addition

to a split ground bus for superior performance.

features

■ 4 kV minimum ESD immunity

■ TTL-compatible inputs

Ordering Code:

Order Number Package Number

Package Description

74ACTQ74SC

74ACTQ74SJ

74ACTQ74PC

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.

Connection Diagram

Pin Descriptions

Pin Names

Description

Data Inputs

D₁, D₂

CP₁, CP₂

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs

C_D1, C_D2

S_D1, S_D2

Q₁, Q₁, Q₂, Q₂

FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.

DS010920

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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与74ACTQ74相关器件

型号	品牌	获取价格	描述	数据表
74ACTQ74PC	FAIRCHILD	获取价格	Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
74ACTQ74PCQR	ETC	获取价格	Dual D-Type Flip-Flop
74ACTQ74SC	FAIRCHILD	获取价格	Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
74ACTQ74SCQR	ETC	获取价格	Dual D-Type Flip-Flop
74ACTQ74SCX	ETC	获取价格	Dual D-Type Flip-Flop
74ACTQ74SCX_NL	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO
74ACTQ74SJ	FAIRCHILD	获取价格	Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
74ACTQ74SJX	FAIRCHILD	获取价格	Dual D-Type Flip-Flop
74ACTQ821	FAIRCHILD	获取价格	Quiet Seriesa⑩ 10-Bit D-Type Flip-Flop with 3
74ACTQ821_00	FAIRCHILD	获取价格	Quiet Series 10-Bit D-Type Flip-Flop with 3-STATE Outputs

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