74ACT715

更新时间： 2024-11-01 22:56:15

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
14页	129K
描述
Programmable Video Sync Generator

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数据手册

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74ACT715 数据手册

November 1988

Revised December 1998

74ACT715•74ACT715-R

Programmable Video Sync Generator

to a Clock Enabled state. Bit 10 of the Status Register

defaults to a logic “1”. Although completely (re)programma-

ble, the ACT715-R version is better suited for applications

using the default 14.31818 MHz RS-170 register values.

This feature allows power-up directly into operation, follow-

ing a single CLEAR pulse.

General Description

The ACT715 and ACT715-R are 20-pin TTL-input compati-

ble devices capable of generating Horizontal, Vertical and

Composite Sync and Blank signals for televisions and

monitors. All pulse widths are completely definable by the

user. The devices are capable of generating signals for

both interlaced and noninterlaced modes of operation.

Equalization and serration pulses can be introduced into

the Composite Sync signal when needed.

Features

■ Maximum Input Clock Frequency > 130 MHz

■ Interlaced and non-interlaced formats available

Four additional signals can also be made available when

Composite Sync or Blank are used. These signals can be

used to generate horizontal or vertical gating pulses, cursor

position or vertical Interrupt signal.

■ Separate or composite horizontal and vertical Sync and

Blank signals available

■ Complete control of pulse width via register

programming

These devices make no assumptions concerning the sys-

tem architecture. Line rate and field/frame rate are all a

function of the values programmed into the data registers,

the status register, and the input clock frequency.

■ All inputs are TTL compatible

■ 8 mA drive on all outputs

■ Default RS170/NTSC values mask programmed into

registers

The ACT715 is mask programmed to default to a Clock

Disable state. Bit 10 of the Status Register, Register 0,

defaults to a logic “0”. This facilitates (re)programming

before operation.

■ ACT715-R is mask programmed to default to a Clock

Enable state for easier start-up into 14.31818 MHz

RS170 timing

The ACT715-R is the same as the ACT715 in all respects

except that the ACT715-R is mask programmed to default

Ordering Code:

Order Number Package Number

Package Description

74ACT715SC

74ACT715PC

74ACT715-RSC

74ACT715-RPC

M20B

N20A

M20B

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignment for DIP and SOIC

FACT is a trademark of Fairchild Semiconductor Corporation.

DS010137.prf

www.fairchildsemi.com

12 3 4 5 6 7...14

中文翻译

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与74ACT715相关器件

型号	品牌	获取价格	描述	数据表
74ACT715_07	FAIRCHILD	获取价格	Programmable Video Sync Generator
74ACT715_1	FAIRCHILD	获取价格	Programmable Video Sync Generator
74ACT715DC	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20
74ACT715FC	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CDFP20, CERAMIC, FP-20
74ACT715FCQR	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CDFP20, CERAMIC, FP-20
74ACT715LCQR	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20
74ACT715LSQR	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, PDSO20, SOIC-20
74ACT715LX	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20
74ACT715PC	FAIRCHILD	获取价格	Programmable Video Sync Generator
74ACT715PCQR	FAIRCHILD	获取价格	Consumer Circuit

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