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74ACT715SC PDF预览

74ACT715SC

更新时间: 2024-11-01 22:56:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 消费电路商用集成电路光电二极管
页数 文件大小 规格书
14页 129K
描述
Programmable Video Sync Generator

74ACT715SC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SOIC-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.57
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm湿度敏感等级:1
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Other Consumer ICs
最大压摆率:0.08 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

74ACT715SC 数据手册

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November 1988  
Revised December 1998  
74ACT715•74ACT715-R  
Programmable Video Sync Generator  
to a Clock Enabled state. Bit 10 of the Status Register  
defaults to a logic “1”. Although completely (re)programma-  
ble, the ACT715-R version is better suited for applications  
using the default 14.31818 MHz RS-170 register values.  
This feature allows power-up directly into operation, follow-  
ing a single CLEAR pulse.  
General Description  
The ACT715 and ACT715-R are 20-pin TTL-input compati-  
ble devices capable of generating Horizontal, Vertical and  
Composite Sync and Blank signals for televisions and  
monitors. All pulse widths are completely definable by the  
user. The devices are capable of generating signals for  
both interlaced and noninterlaced modes of operation.  
Equalization and serration pulses can be introduced into  
the Composite Sync signal when needed.  
Features  
Maximum Input Clock Frequency > 130 MHz  
Interlaced and non-interlaced formats available  
Four additional signals can also be made available when  
Composite Sync or Blank are used. These signals can be  
used to generate horizontal or vertical gating pulses, cursor  
position or vertical Interrupt signal.  
Separate or composite horizontal and vertical Sync and  
Blank signals available  
Complete control of pulse width via register  
programming  
These devices make no assumptions concerning the sys-  
tem architecture. Line rate and field/frame rate are all a  
function of the values programmed into the data registers,  
the status register, and the input clock frequency.  
All inputs are TTL compatible  
8 mA drive on all outputs  
Default RS170/NTSC values mask programmed into  
registers  
The ACT715 is mask programmed to default to a Clock  
Disable state. Bit 10 of the Status Register, Register 0,  
defaults to a logic “0”. This facilitates (re)programming  
before operation.  
ACT715-R is mask programmed to default to a Clock  
Enable state for easier start-up into 14.31818 MHz  
RS170 timing  
The ACT715-R is the same as the ACT715 in all respects  
except that the ACT715-R is mask programmed to default  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACT715SC  
74ACT715PC  
74ACT715-RSC  
74ACT715-RPC  
M20B  
N20A  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignment for DIP and SOIC  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010137.prf  
www.fairchildsemi.com  

74ACT715SC 替代型号

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