March 1995
LM1882 54ACT/74ACT715
#
LM1882-R 54ACT/74ACT715-R
#
Programmable Video Sync Generator
’ACT715-R/LM1882-R is mask programmed to default to a
Clock Enabled state. Bit 10 of the Status Register defaults
to a logic ‘‘1’’. Although completely (re)programmable, the
’ACT715-R/LM1882-R version is better suited for applica-
tions using the default 14.31818 MHz RS-170 register val-
ues. This feature allows power-up directly into operation,
following a single CLEAR pulse.
General Description
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are
20-pin TTL-input compatible devices capable of generating
Horizontal, Vertical and Composite Sync and Blank signals
for televisions and monitors. All pulse widths are completely
definable by the user. The devices are capable of generat-
ing signals for both interlaced and noninterlaced modes of
operation. Equalization and serration pulses can be intro-
duced into the Composite Sync signal when needed.
Features
Y
Y
Y
l
130 MHz
Maximum Input Clock Frequency
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
Interlaced and non-interlaced formats available
Separate or composite horizontal and vertical Sync and
Blank signals available
Y
Complete control of pulse width via register
programming
These devices make no assumptions concerning the sys-
tem architecture. Line rate and field/frame rate are all a
function of the values programmed into the data registers,
the status register, and the input clock frequency.
Y
Y
Y
All inputs are TTL compatible
8 mA drive on all outputs
Default RS170/NTSC values mask programmed into
registers
The ’ACT715/LM1882 is mask programmed to default to a
Clock Disable state. Bit 10 of the Status Register, Register
0, defaults to a logic ‘‘0’’. This facilitates (re)programming
before operation.
Y
Y
4 KV minimum ESD immunity
’ACT715-R/LM1882-R is mask programmed to default
to a Clock Enable state for easier start-up into
14.31818 MHz RS170 timing
The ’ACT715-R/LM1882-R is the same as the
’ACT715/LM1882 in all respects except that the
Connection Diagrams
Pin Assignment for
DIP and SOIC
Pin Assignment
for LCC
TL/F/10137–1
Order Number LM1882CN or LM1882CM
For Default RS-170, Order Number LM1882-RCN or
LM1882-RCM
TL/F/10137–2
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/10137
RRD-B30M105/Printed in U. S. A.