74ACT273SCTR

更新时间： 2024-01-25 11:58:35

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
10页	101K
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数据手册

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74ACT273SCTR 数据手册

November 1988

Revised August 2000

74AC273 • 74ACT273

Octal D-Type Flip-Flop

General Description

Features

■ Ideal buffer for microprocessor or memory

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

The AC273 and ACT273 have eight edge-triggered D-type

flip-flops with individual D-type inputs and Q outputs. The

common buffered Clock (CP) and Master Reset (MR) input

load and reset (clear) all flip-flops simultaneously.

■ Buffered, asynchronous master reset

■ See 377 for clock enable version

■ See 373 for transparent latch version

■ See 374 for 3-STATE version

The register is fully edge-triggered. The state of each D-

type input, one setup time before the LOW-to-HIGH clock

transition, is transferred to the corresponding flip-flop’s Q

output.

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input. The

device is useful for applications where the true output only

is required and the Clock and Master Reset are common to

all storage elements.

■ Outputs source/sink 24 mA

■ 74ACT273 has TTL-compatible inputs

Ordering Code:

Order Number Package Number

Package Description

74AC273SC

74AC273SJ

M20B

M20D

MTC20

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC273MTC

74AC273PC

74ACT273SC

74ACT273SJ

74ACT273MTC

74ACT273PC

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

M20B

M20D

MTC20

N20A

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

FACT is a trademark of Fairchild Semiconductor Corporation.

DS009954

www.fairchildsemi.com

12 3 4 5 6 7...10

中文翻译

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与74ACT273SCTR相关器件

型号	品牌	获取价格	描述	数据表
74ACT273SCX	FAIRCHILD	获取价格	Octal D-Type Flip-Flop
74ACT273SCX_NL	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20
74ACT273SCXR	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20
74ACT273SJ	FAIRCHILD	获取价格	Octal D-Type Flip-Flop
74ACT273SJX	FAIRCHILD	获取价格	Octal D-Type Flip-Flop
74ACT273T	STMICROELECTRONICS	获取价格	OCTAL D-TYPE FLIP FLOP WITH CLEAR
74ACT273TTR	ETC	获取价格	Octal D-Type Flip-Flop
74ACT280	STMICROELECTRONICS	获取价格	9 BIT PARITY GENERATOR/CHECKER
74ACT280B	STMICROELECTRONICS	获取价格	9 BIT PARITY GENERATOR/CHECKER
74ACT280M	STMICROELECTRONICS	获取价格	9 BIT PARITY GENERATOR/CHECKER