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74ACT280M PDF预览

74ACT280M

更新时间: 2024-11-30 22:40:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 运算电路逻辑集成电路光电二极管
页数 文件大小 规格书
8页 65K
描述
9 BIT PARITY GENERATOR/CHECKER

74ACT280M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SO-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.33
Is Samacsys:N系列:ACT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm逻辑集成电路类型:PARITY GENERATOR/CHECKER
湿度敏感等级:1位数:9
功能数量:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
传播延迟(tpd):14.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Arithmetic Circuits
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

74ACT280M 数据手册

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74ACT280  
9 BIT PARITY GENERATOR/CHECKER  
HIGH SPEED:tPD =4 ns (TYP.) atVCC =5V  
LOW POWER DISSIPATION:  
CC =4 µA (MAX.) at TA =25 oC  
I
COMPATIBLEWITH TTL OUTPUTS  
VIH =2V (MIN), VIL = 0.8V(MAX)  
50TRANSMISSIONLINEDRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 24 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
B
M
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
74ACT280B  
74ACT280M  
nine data inputs control the output conditions.  
When the number of high level input is odd,  
ΣODD output is kept high and ΣEVEN output low.  
Conservely, when the output is even, EVEN  
output is kept high and ΣODD low.  
The IC generates either odd or even parity  
making it flexible application.  
The word-length capability is easily expanded by  
cascading.  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
VCC (OPR)= 4.5V to 5.5V  
Σ
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES280  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The AC280 is an advanced high-speed CMOS 9  
BIT PARITY GENERATOR  
fabricated with sub-micron silicon gate and  
double-layer metal wiring C2MOS technology.It is  
ideal for low power applications mantaining high  
speed operation similar to eqivalent Bipolar  
SchottkyTTL.  
It is composed of nine data inputs (A to I) and  
odd/even parity outputs ( ODD and EVEN). The  
-
CHECKER  
Σ
Σ
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
December 1998  

74ACT280M 替代型号

型号 品牌 替代类型 描述 数据表
CD74ACT280M96G4 TI

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